Today’s technology nodes contain more and more complex designs bringing increasing challenges to chip manufacturing process steps. It is necessary to have an efficient metrology to assess process variability of these complex patterns and thus extract relevant data to generate process aware design rules and to improve OPC models. Today process variability is mostly addressed through the analysis of in-line monitoring features which are often designed to support robust measurements and as a consequence are not always very representative of critical design rules. CD-SEM is the main CD metrology technique used in chip manufacturing process but it is challenged when it comes to measure metrics like tip to tip, tip to line, areas or necking in high quantity and with robustness. CD-SEM images contain a lot of information that is not always used in metrology. Suppliers have provided tools that allow engineers to extract the SEM contours of their features and to convert them into a GDS. Contours can be seen as the signature of the shape as it contains all the dimensional data. Thus the methodology is to use the CD-SEM to take high quality images then generate SEM contours and create a data base out of them. Contours are used to feed an offline metrology tool that will process them to extract different metrics. It was shown in two previous papers that it is possible to perform complex measurements on hotspots at different process steps (lithography, etch, copper CMP) by using SEM contours with an in-house offline metrology tool. In the current paper, the methodology presented previously will be expanded to improve its robustness and combined with the use of phylogeny to classify the SEM images according to their geometrical proximities.
SEM images provide valuable information about patterning capability. Geometrical properties such as Critical Dimension (CD) can be extracted from them and are used to calibrate OPC models, thus making OPC more robust and reliable. However, there is currently a shortage of appropriate metrology tools to inspect complex two-dimensional patterns in the same way as one would work with simple one-dimensional patterns. In this article we present a full framework for the analysis of SEM images. It has been proven to be fast, reliable and robust for every type of structure, and particularly for two-dimensional structures. To achieve this result, several innovative solutions have been developed and will be presented in the following pages. Firstly, we will present a new noise filter which is used to reduce noise on SEM images, followed by an efficient topography identifier, and finally we will describe the use of a topological skeleton as a measurement tool that can extend CD measurements on all kinds of patterns.
Recent industrial results around directed self-assembly (DSA) of block copolymers (BCP) have demonstrated the high potential of such technique. One of the main advantages of this method is the reduction of lithographic steps thus leading to cost reduction. At the same time, the associated correction for mask creation must account for the introduction of this new technique maintaining a high level of accuracy and reliability. In order to create a Vertical Interconnect Layer (VIA) layer, graphoepitaxy DSA is the main candidate. The technique relies on the creation of a confinement guide where the BCP can separate into distinct regions and the resulting patterns are etched in order to obtain an ordered contact layer. The printing of the guiding pattern requires a classical lithography and optical proximity correction (OPC) to obtain the best suited guiding pattern for a specific target. Thus it is necessary to perform simulations of the BCP behavior in order to correctly determine contact hole placement. However, most existing models which simulates the BCP phase segregation have a computational cost that is too high and cannot be used to efficiently correct a full layout. In this study, we propose an original compact model that resolves this issue. The model is based on the calculation of the density probability of PMMA (Polymethyl Methacrylate) domain centers (figure 1). It is compared with both rigorous simulations (based on the Otha-Kawasaki model) and experiments as shown in figure 2. For this analysis, test cases are contact shrink and contact multiplication. The number of PMMA domains inside a structure is also discussed and an analytic formula is derived and compared to experiments (figure 3). The overall consistency of the compact model is presented.
For technologies beyond 10 nm, 1D gridded designs are commonly used. This practice is common particularly in the case of Self-Aligned Double Patterning (SADP) metal processes where Vertical Interconnect Access (VIA) connecting metal line layers are placed along a discrete grid thus limiting the number of VIA pitches. In order to create a Vertical Interconnect Access (VIA) layer, graphoepitaxy Directed Self-Assembly (DSA) is the prevailing candidate. The technique relies on the creation of a confinement guide using optical microlithography methods, in which the BCP is allowed to separate into distinct regions. The resulting patterns are etched to obtain an ordered VIA layer.
Guiding pattern variations impact directly on the placement of the target and one must ensure that it does not interfere with circuit performance. To prevent flaws, design rules are set. In this study, for the first time, an original framework is presented to find a consistent set of design rules for enabling the use of DSA in a production flow using Self Aligned Double Patterning (SADP) for metal line layer printing.
In order to meet electrical requirements, the intersecting area between VIA and metal lines must be sufficient to ensure correct electrical connection. The intersecting area is driven by both VIA placement variability and metal line printing variability. Based on multiple process assumptions for a 10 nm node, the Monte Carlo method is used to set a maximum threshold for VIA placement error.
In addition, to determine a consistent set of design rules, representative test structures have been created and tested with our in-house placement estimator: the topological skeleton of the guiding pattern . Using this technique, structures with deviation above the maximum tolerated threshold are considered as infeasible and the appropriate set of design rules is extracted. In a final step, the design rules are verified with further test structures that are randomly generated using percolation in order to emulate a Placed and Routed (P&R) standard cell block.
Today's design for photonics devices on silicon relies on non-Manhattan features such as curves and a wide variety of angles with minimum feature size below 100nm. Industrial manufacturing of such devices requires optimized process window with 193nm lithography. Therefore, Resolution Enhancement Techniques (RET) that are commonly used for CMOS manufacturing are required.
However, most RET algorithms are based on Manhattan fragmentation (0°, 45° and 90°) which can generate large CD dispersion on masks for photonic designs. Industrial implementation of RET solutions to photonic designs is challenging as most currently available OPC tools are CMOS-oriented. Discrepancy from design to final results induced by RET techniques can lead to lower photonic device performance.
We propose a novel sizing algorithm allowing adjustment of design edge fragments while preserving the topology of the original structures. The results of the algorithm implementation in the rule based sizing, SRAF placement and model based correction will be discussed in this paper. Corrections based on this novel algorithm were applied and characterized on real photonics devices. The obtained results demonstrate the validity of the proposed correction method integrated in Inscale software of Aselta Nanographics.
Recent industrial results around directed self-assembly (DSA) of block copolymers (BCP) have demonstrated the high potential of this technique [1-2]. The main advantage being cost reduction thanks to a reduced number of lithographic steps. Meanwhile, the associated correction for mask creation must account for the introduction of this new technique, maintaining a high level of accuracy and reliability. In order to create VIA (Vertical Interconnect Layer) layer, graphoepitaxy DSA can be used. The technique relies on the creation of a confinement guides where the BCP can separate into distinct regions and resulting patterns are etched in order to obtain an ordered series of VIA contact. The printing of the guiding pattern requires the use of classical lithography. Optical proximity correction (OPC) is applied to obtain the best suited guiding pattern allowing to match a specific design target.
In this study, an original approach for DSA full chip mask optical proximity correction based on a skeleton representation of a guiding pattern is proposed. The cost function for an OPC process is based on minimizing the Central Placement Error (CPE), defined as the difference between an ideal skeleton target and a generated skeleton from a guiding contour. The high performance of this approach for DSA OPC full chip correction and its ability to minimize variability error on via placement is demonstrated and reinforced by the comparison with a rigorous model. Finally this Skeleton approach is highlighted as an appropriate tool for Design rules definition.