Mr. Loïc Schneider Profile

Loïc Schneider

at STMicroelectronics

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Publications (6)

Proceedings Article | 28 September 2017 Paper

Advanced metrology by offline SEM data processing

Amine Lakcher, Loïc Schneider, Bertrand Le-Gratiet, Julien Ducoté, Vincent Farys, Maxime Besacier

Proc. SPIE. 10446, 33rd European Mask and Lithography Conference

KEYWORDS: Lithography, Metrology, Etching, Inspection, Scanning electron microscopy, Data processing, Process control

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Proceedings Article | 28 March 2017 Presentation + Paper

Framework for SEM contour analysis

L. Schneider, V. Farys, E. Serret, C. Fenouillet-Beranger

Proc. SPIE. 10145, Metrology, Inspection, and Process Control for Microlithography XXXI

KEYWORDS: Metrology, Optical lithography, Sensors, Image processing, Digital filtering, Denoising, Image analysis, Scanning electron microscopy, Process control, Image filtering, Optical proximity correction, Critical dimension metrology

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Proceedings Article | 22 March 2016 Paper

New placement estimator for contact hole printed with DSA

L. Schneider, V. Farys, E. Serret, C. Fenouillet-Beranger

Proc. SPIE. 9777, Alternative Lithographic Technologies VIII

KEYWORDS: Lithography, Polymethylmethacrylate, Particles, Reliability, Computer simulations, Scanning electron microscopy, Printing, Directed self assembly, Optical proximity correction, Picosecond phenomena, Analytical research, Probability theory

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Proceedings Article | 16 March 2016 Paper

Enablement of DSA for VIA layer with a metal SIT process flow

L. Schneider, V. Farys, E. Serret, C. Fenouillet-Beranger

Proc. SPIE. 9781, Design-Process-Technology Co-optimization for Manufacturability X

KEYWORDS: Lithography, Optical lithography, Nano opto mechanical systems, Metals, Error analysis, Manufacturing, Reliability, Printing, Monte Carlo methods, Photomasks, Directed self assembly, Double patterning technology, Optical proximity correction, Design for manufacturability

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For technologies beyond 10 nm, 1D gridded designs are commonly used. This practice is common particularly in the case of Self-Aligned Double Patterning (SADP) metal processes where Vertical Interconnect Access (VIA) connecting metal line layers are placed along a discrete grid thus limiting the number of VIA pitches. In order to create a Vertical Interconnect Access (VIA) layer, graphoepitaxy Directed Self-Assembly (DSA) is the prevailing candidate. The technique relies on the creation of a confinement guide using optical microlithography methods, in which the BCP is allowed to separate into distinct regions. The resulting patterns are etched to obtain an ordered VIA layer.

Guiding pattern variations impact directly on the placement of the target and one must ensure that it does not interfere with circuit performance. To prevent flaws, design rules are set. In this study, for the first time, an original framework is presented to find a consistent set of design rules for enabling the use of DSA in a production flow using Self Aligned Double Patterning (SADP) for metal line layer printing.

In order to meet electrical requirements, the intersecting area between VIA and metal lines must be sufficient to ensure correct electrical connection. The intersecting area is driven by both VIA placement variability and metal line printing variability. Based on multiple process assumptions for a 10 nm node, the Monte Carlo method is used to set a maximum threshold for VIA placement error.

In addition, to determine a consistent set of design rules, representative test structures have been created and tested with our in-house placement estimator: the topological skeleton of the guiding pattern [1]. Using this technique, structures with deviation above the maximum tolerated threshold are considered as infeasible and the appropriate set of design rules is extracted. In a final step, the design rules are verified with further test structures that are randomly generated using percolation in order to emulate a Placed and Routed (P&R) standard cell block.

Proceedings Article | 15 March 2016 Paper

OPC for curved designs in application to photonics on silicon

Bastien Orlando, Vincent Farys, Loïc Schneider, Sébastien Cremer, Sergei Postnikov, Matthieu Millequant, Mathieu Dirrenberger, Charles Tiphine, Sébastian Bayle, Céline Tranquillin, Patrick Schiavone

Proc. SPIE. 9780, Optical Microlithography XXIX

KEYWORDS: Lithography, Photonic devices, Waveguides, Silicon, Scanning electron microscopy, Photonics, Optical proximity correction, SRAF, Silicon photonics, Resolution enhancement technologies

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Proceedings Article | 4 September 2015 Paper

Skeleton-based OPC application for DSA full chip mask correction

L. Schneider, V. Farys, E. Serret, C. Fenouillet-Beranger

Proc. SPIE. 9661, 31st European Mask and Lithography Conference

KEYWORDS: Lithography, Polymethylmethacrylate, Metals, Reliability, Scanning electron microscopy, Printing, Photomasks, Directed self assembly, Optical proximity correction, Performance modeling

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Showing 5 of 6 publications

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