Prof. Louis-Pierre Armellin Profile

Prof. Louis-Pierre Armellin

DUV Coordinator

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Publications (4)

Proceedings Article | 20 March 2006 Paper

Illumination conditions matching for critical layers manufacturing in a production context

Louis-Pierre Armellin, Andreas Torsy, Ken Hernan, Gurwan Kerrien, Johanna Guidet, Yan Riopel, Vincent Salvetat

Proceedings Volume 6154, 61543V (2006) https://doi.org/10.1117/12.656538

KEYWORDS: Optical proximity correction, Scanners, Fiber optic illuminators, Semiconducting wafers, Lithography, Relays, Scanning electron microscopy, Manufacturing, Critical dimension metrology, Lithographic illumination

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As device geometries shrink, the lithography solutions to satisfy production requirements for a manufacturable process window often includes Optical Proximity Correction (OPC). OPC is sensitive to many process parameters, one of the most important is the illumination condition, this implicitly includes the lens NA and illuminator NA that generate the partial coherence factor σ, of the scanner. In a production context, the same performance is required for the product using several exposure tools but only one OPC scheme; this requires that the illumination conditions between scanners are matched. This verification has to be done not only for tools of the same generation, but the more complex case between tools of different generations. For the gate layer, an important requirement is the Across Chip Linewidth Variation (ACLV) that ensures transistors performance whatever the pitch. This requirement is mainly driven by Nested-Iso Bias. The paper will present the work completed on the gate layer in order to match the illumination conditions between scanners of the same generation and also between two scanners of different generations: one offers 0.68NA and a maximum σ of 0.75, the other has a maximum NA of 0.82 and maximum σ of 0.9. For scanners of the same generation, the matching was done by simply measuring the illumination NA of the tools, and for this a pinhole test was used. The matching was verified after litho by measuring Nested-Iso bias, and then on product using electrical CD measurement. For the "generation matching", two parameters are needed to define the illumination conditions: lens NA and illuminator NA. In this case, Nested-Iso bias is insufficient to identify the matching conditions as several combinations of lens and illuminator NA lead to the same Nested-Iso bias. Instead the OPC was checked on proximity curves generated for line end shortening and SRAM cells. The best matching conditions were then optimised using a simulation tool with the final check completed on product using electrical CD measurement.

Proceedings Article | 15 March 2006 Paper

DOF enhancement for contact holes by using Nikon's CDP option and its introduction into production

Louis-Pierre Armellin, Virginie Dureuil, Laurent Nuel, Vincent Salvetat, Winfried Meier, Andreas Kraft

Proceedings Volume 6154, 61542B (2006) https://doi.org/10.1117/12.656522

KEYWORDS: Semiconducting wafers, Scanners, Finite element methods, Manufacturing, Optical lithography, Yield improvement, Logic, Optical engineering, Objectives, Standards development

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Proceedings Article | 15 March 2006 Paper

Evaluation of an advanced process control solution to detect wafer positioning issues within the hot and cold plate modules of a lithography track

Olivier Guillaume, Marc Bouchardy, Louis-Pierre Armellin

Proceedings Volume 6155, 61550K (2006) https://doi.org/10.1117/12.655573

KEYWORDS: Semiconducting wafers, Temperature metrology, Process control, Chemical elements, Lithography, Wafer testing, Robotics, Sensors, Data communications, Critical dimension metrology

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Proceedings Article | 10 May 2005 Paper

Separating cluster contribution to improve CD distribution using simultaneous dose-focus monitoring on production wafers

Louis-Pierre Armellin, Virginie Dureuil, Olivier Guillaume, Philippe Alet, Brad Eichelberger, Michel Egreteau, Marco Polli, Berta Dinu

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.598045

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Scanners, Scanning electron microscopy, Finite element methods, Calibration, Control systems, Diagnostics, Temperature metrology, Statistical modeling

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