Two different drain field relief architectures, lightly doped drain (LDD) and gate overlapped LDD (GOLDD), for polysilicon TFT have been analyzed and compared to conventional self-aligned (SA) devices. The introduction of LDD regions improves off-current, kink effect and electrical stability if compared to SA devices. However, a parasitic resistance effect is also introduced, thus limiting the benefits of LDD structures. GOLDD architecture overcomes this drawback, but, more importantly, show improved off-current and kink effect and exceptionally high electrical stability. The experimental results have been explained by analyzing the electric field distributions, obtained by two-dimensional numerical simulations, while a new tool to explain hot-carrier induced modifications in polysilicon TFTs was developed.
Polysilicon thin-film transistors are of great interest for their application in large area microelectronics and especially for their circuit applications. A successful circuit design requires a proper understanding of the electrical characteristics and in the present work some specific aspects related to the presence of high electric fields at the drain end of the channel are presented.