This paper describes the design of a programmable stand-alone system for real time vision pre-processing tasks. The system's architecture has been implemented and tested using an ACE16k chip and a Xilinx xc4028xl FPGA. The ACE16k chip consists basically of an array of 128x128 identical mixed-signal processing units, locally interacting, which operate in accordance with single instruction multiple data (SIMD) computing architectures and has been designed for high speed image pre-processing tasks requiring moderate accuracy levels (7 bits). The input images are acquired using the optical input capabilities of the ACE16k chip, and after being processed according to a programmed algorithm, the images are represented at real time on a TFT screen. The system is designed to store and run different algorithms and to allow changes and improvements. Its main board includes a digital core, implemented on a Xilinx 4028 Series FPGA, which comprises a custom programmable Control Unit, a digital monochrome PAL video generator and an image memory selector. Video SRAM chips are included to store and access images processed by the ACE16k. Two daughter boards hold the program SRAM and a video DAC-mixer card is used to generate composite analog video signal.
This paper describes the architecture and retino-topic unit of a bio-inspired vision chip intended for automotive applications. The chip contains an array of 100X150 sensors which are able to capture high dynamic range (HDR) images, with a programmable compressive characteristic. The chip also incorporates a mechanism for adaptation of the global exposition time to the average illumination conditions. Average values are evaluated over image areas which are programmable by the user. In addition to the HDR pixel, every retino-topic unit in the array incorporates digital memory for three 6-bit pixel values (18-bits), as required for the implementation of a bionspired computing model for collisions detection which has been developed in the framework of a multidisciplinary European research project. All processing steps are executed off-chip, though we are currently working in the design of tiny digital processors (one per column) which will allow for running the whole model on-chip in a future version of this prototype. The chip has been designed in a 0.35μm 2P-4M technology and maintains its correct operation in extreme temperature conditions (from -40°C to 110°C).