Control of the transistor gate critical dimension (CD) on the order of a few nanometers is a top priority in many advanced fabs like Chartered. Each nanometer deviation from the targeted gate length implicitly means that the operational speed of the devices are also affected. In transistors, for example, when the post-etch gate CD is too small, the threshold voltage shift and leakage current can render the device inoperative. Increasingly, advances in logic devices are requiring technological improvements, and fab economics are necessitating greater productivity. In an automated foundry environment, the target gate CD can be achieved in more than one way. For example, using in-line process control by linking the lithography and etch tools can improve CD performance beyond what each individual tool can achieve. In this approach, the etch process is used to compensate for incoming CD variation and reduce final wafer-to-wafer CD variation. However, this feed-forward approach of CD control involves a one-time heavy investment in integrated optical CD (OCD) metrology as well as an integrated server to feedback process control that will automatically adjust tools and process steps in high-volume, wafer-fabrication lines. The other considerations are the time involved in retrofitting and the complexity of qualifying these integrated tools after retrofit. A second way to do it is to change the sigma slightly to match tool to tool. But by so doing, process window parameters like DOF and such are also affected. This technique is adopted by many ASML users as the new ASML illumination setting (new NA/Sigma) is fairly easy to set up. However, the problem is that it makes the system unmanageable on large scale especially in a foundry environment. The work done here involves seeking a more economical approach of CD control without modifying the hardware of existing tool set to pave the path for a more demanding CD matching requirement between lithography tools. It is necessary not only to ensure the same process exposure conditions used from different tools to achieve a good CD matching for large scale manufacturing, but also to ensure the same CD matching performance for some critical pitches if not all. This is important for a foundry which runs a myraid range of products having different line pitches for different gate layers. DUV optical lithography has met the shrinking CD requirements for 0.13um technology node. The introduction of Optical Proximity Correction (OPC) on the reticle, has further prolonged the binary mask life. The procedure provided herein attempts to render tool dedication as a result of non-compatibility of OPC design rule unnecessary. In this paper, the authors will present the challenges faced in the course of matching the lithography tool set for the large scale manufacturability in terms of stepper energy and iso-dense CD bias, such that the exposure dose requested and the real dose applied on the wafer level is the same for any one process tool set and is within the tolerable range of iso-dense CD bias of 4nm.
As critical-dimension shrink below 0.18 μm, the SPC (Statistical Process Control) based CD (Critical Dimension) control in lithography process becomes more difficult. Increasing requirements of a shrinking process window have called on the need for more accurate process control. So Advanced Process Control (APC) is going to be a must in the future deep sub-micron lithography, especially 0.18 μm and below. Successful implementation of APC into photolithography depends on how accurate we can determine exposure and defocus from in-line production wafer. Traditionally, in-line process control is based on single structure CD measurement, normally of the smallest dimension as per design. However single import is not enough to predict exposure and focus drift simultaneously. So a lot of studies were done on how to extract exposure and defocus information from in-line CD measurements. And one of these methods is to distinguish focus from energy by monitoring multi-structure CD (CDs of iso/dense, line/pillar and space/hole etc) on normal production wafer. In this paper, we will give a description of this concept. And from that we can see the advantages and drawbacks of this method. Photolithography Simulations (on Prolith) will be carried out to understand the problems we are facing to implement this method into tool matching and inline process control. Finally, we will also propose a new approach to overcome the drawbacks of this method.
As critical-dimension (CD) shrink below 0.18um, CD control becomes a major concern. Normally there are four approaches to improve CD control: to improve intra-field, intra-wafer, inter-wafer and inter-lot CD uniformity. In this paper, we propose a simple method to improve intra-wafer CD uniformity by optimize developing recipe. In DUV photolithography, intra-wafer CD variation is the major contributor to the overall CD variations. However there are many factors that may impact intra-wafer CD uniformity: Photoresist thickness uniformity, PEB uniformity, wafer surface roughness, substrate reflectivity and developing uniformity, so the situation become very complicated. In our studies, we tried to focus mainly on the developing uniformity of DUV process. To isolate the impact of developing method from other process factors, we proposed a simple method to check developing rate (Rmin) uniformity by photoresist thickness measurement. With this method, we had save a lot of time and manpower in developing recipe tuning and also had a deeper understanding of developing process of DUV resist.
The increasing of wafer size from 200mm to 300mm and downscaling of IC design rule has imposed increasingly tighter overlay tolerances, which becomes very challenging at the 100 nm lithographic node. Such tight tolerances will require very high performance in alignment and overlay measurement. In this paper, we present a concept of total process control of alignment and overlay, which we had used to get deeper understanding of our metal process with W-CMP and aluminum sputter. Traditionally, a lot of works are focusing on alignment process control and overlay process control separately. However, based on what we had observed, the final overlay performance is largely affected by the difference between alignment system (alignment mark, alignment sensor and process) and overlay system (overlay mark, overlay sensor and process). Deeper understanding of this difference between alignment and overlay system do help us to get better overlay process control o and process/tool matching.
Satellite spots defects of size less than 1um are being experienced with UV series positive deep-UV photo resists at Chartered and it is believed to be formed as a result of the insoluble resist residue remaining on the BARC after the developing process. Though these defects reported are by far cosmetic defects that are not transferred after etch, we expect the results presented here to be significant and applicable to smaller geometries and to 12-inch wafer fabs. Figure 1 shows a typical satellite spots defect found in the open area where there are no resist patterns after the developing process. The spinning cycle of the developing process is thought to make the aqueous resist-developer dissolution adhere to the surface of the BARC in a satellite-like formation. In a small geometry on a patterned wafer under microgravity environment, the Marangoni convection occurs in the thin resist-developer dissolution during developing causing the micro dry spots in the dissolution under the spreading developer. The high surface tension of the deep-UV resists is believed to make it more difficult to remove after the hard bake process. The probabilistic model for the mechanism of resist-developer dissolution provides a theoretical backing to the resolution of satellite spots defect and it adequately accounts for the dissolution behavior of poly (hydroxystyrene) (PHS). Different developing recipes ranging from DI-water pre-wet, developer pre-wet, to high spin speed during DIW rinse were being investigated to find out the effectiveness in removing satellite spots. The combination of extended DIW rinse time, without resorting to high spin speed or high acceleration, and double developer puddling programs produce the lowest counts with the TMAH developer. Considerable defect density improvement after the developing process can be realized using the above control methodology. Although no significant yield improvement can be achieved at the present 0.25micrometers technology in Chartered, we believe that the results presented here will become significant as the Company moves towards smaller geometries.