A cost-efficient technique for full-chip source and mask optimization is proposed in this paper. This technique has two
components: SMO source optimization for full-chip and flexible mask optimization (FMO). During the technology
development stage of source optimization, a novel pattern-selection technique was used to identify critical clips from a
full-set of design clips; SMO was then used to optimize the source based on those selected critical-clips. This pattern-selection
technique enables reasonable SMO runtime to optimize the source that covers the full range of patterns. During
the process development stage and product tapeout stage, FMO is employed. The FMO framework allows the use of
different OPC computational techniques on different chip areas that have different sensitivities to process variations.
Advanced OPC methods are applied only where they are needed, therefore achieving optimum process performance with
the least tapeout and mask cost.
In this paper the co-optimization of the source, mask, and design is discussed. In particular the printing of the pdBRIX logic
templates and SRAM cell is investigated through Tachyon SMO for the contact and metal 1 layer. Both the SRAM and
pdBRIX logic templates were designed for the 22nm logic node with a 40nm half-pitch. The source and mask were
optimized for an ASML /1950 at maximum NA of 1.35 and with FlexRay illumination. The use of pdBRIX logic templates
are designed on a regular fabric consistent with the SRAM to enable process window improvement as well as faster
convergence of SMO with the desired effect of reducing the lithographic process development time. To this end, various
feedback loops in the design and lithography co-optimization are considered. All these feedback loops were eliminated by
studying both the SRAM layout with random logic created from pdBRIX templates. One feedback loop of insufficient
process window (PW) for the contact layer is corrected by using a bright field mask and negative process which increases the
PW area by three times. The improper coloring of a contact hole layer through double patterning is found through SMO, and
corrected by modifying the color scheme. A redesign of the SRAM while preserving the area of the SRAM cell is suggested
by SMO in which the redesign improves the PW by 19.5%. Finally, we discuss the improvement in PW for simultaneous
SMO on pdBRIX logic and SRAM.
This paper investigates the application of source-mask optimization (SMO) techniques for 28 nm logic device and
beyond. We systematically study the impact of source and mask complexity on lithography performance. For the source,
we compare SMO results for the new programmable illuminator (ASML's FlexRay) and standard diffractive optical
elements (DOEs). For the mask, we compare different mask-complexity SMO results by enforcing the sub-resolution
assist feature (SRAF or scattering bar) configuration to be either rectangular or freeform style while varying the mask
manufacturing rule check (MRC) criteria. As a lithography performance metric, we evaluate the process windows and
MEEF with different source and mask complexity through different k<sub>1</sub> values. Mask manufacturability and mask writing
time are also examined. With the results, the cost effective approaches for logic device production are shown, based on
the balance between lithography performance and source/mask (OPC/SRAF) complexity.
The co-optimization of the source and mask patterns [1, 2] is vital to future advanced ArF technology node
development. This paper extends work previously reported on this topic [3, 4]. We will systematically study the impact
of source on designs with different k<sub>1</sub> values using SMO. Previous work compared the co-optimized versus iterative
source-mask optimization methods . We showed that the co-optimization method clearly improved lithography
performance. This paper's approach consists of: 1) Co-optimize a pixelated freeform source and a continuous transmission gray tone mask based on a user specified cost function; 2) ASML-certified scanner-specific models and constraints are applied to the optimized source; 3) Assist feature (AF) "seeds" are identified from the optimized continuous transmission mask (CTM). Both the
AF seed and the main feature are subsequently converted into a polygon mask; 4) The extracted AF seeds and main features are co-optimized with the source to achieve the best lithographic
performance. Using this approach, we first use a DRAM brick wall design to demonstrate that using the same cost function metric by adjusting the optimization conditions creates an image log slope only optimization that can easily be applied. An optimize design for imaging methodology is introduced and shown to be important for low k<sub>1</sub> imaging. A typical 2x node SRAM design is used to illustrate an integrated SMO design rule optimization flow. We use the same SRAM layout that used design rule optimization to study the source complexity impact with a range of k<sub>1</sub> values that varies from 0.42 to 0.35. For the source type, we use freeform and traditional finite pole shape DOEs, all subject to ASML's
scanner-specific models and constraints. We report the process window, MEF and process variation band (PV band)
with different source types to find which source type give the best lithography performance.
Accurate modeling of EUV Lithography is a mandatory step in driving the technology towards its foreseen insertion
point for 22-16nm node patterning. The models are needed to correct EUV designs for imaging effects, and to
understand and improve the CD fingerprint of the exposure tools. With a full-field EUV ADT from ASML now
available in the IMEC cleanroom, wafer data can be collected to calibrate accurate models and check if the existing
modeling infrastructure can be extended to EUV lithography. As a first topic, we have measured the CD on wafer of a
typical OPC dataset at different flare levels and modeled the evolution of wafer CD through flare, reticle CD, and pitch
using Brion's Tachyon OPC engine. The modeling first requires the generation of a flare map using long-range kernels
to model the EUV specific long-range flare. The accuracy of the flare map can be established independently from the CD
measurements, by using the traditional disappearing pad test for flare determination (Kirk test). The flare map is then
used as background intensity in the calibration of the traditional optical models with short-range kernels. For a structure
set of 600 features and over a flare range of 4-6%, an rms fit value of 0.9nm was obtained.
As a second aspect of the modeling, we have calibrated a full resist model to process window data. The full resist model
is then used in a combination with experimental measurements of reticle CD, slit intensity uniformity, focal plane
behavior, and EUV thick mask effects to model the evolution of wafer CD across the exposure field. The modeled
evolution of CD across the exposure field was found to be a good match to the experimentally seen evolution of CD
across the field, and confirms that the 4 factors mentioned above are main contributions to the CD uniformity across the
field. As such the modeling work enables a better understanding of the errors contributing to CD variation across the
field for EUV technology.
When k1 is smaller than the resolution limit, e.g., for a half-pitch (HP) ≤32nm, the most advanced immersion scanner does not have sufficient imaging capability. Extreme ultraviolet (EUV) technology at wavelength of 13.5nm is considered a practical light source for next-generation lithographic technology [1,2]. However, before EUV lithography is suited to mass production, an appropriate exposure technology is needed to fill the gap between immersion ArF and EUV scanners. Double patterning technology (DPT) is a technology that extends the usability of immersion ArF systems. Notably, DPT relaxes the minimum pitch of a circuit layout for each split exposure; thus, ArF water-based immersion systems can be extended to 32 nm node and beyond. Improvements to exposure system hardware are needed to enhance imaging, overlay, and productivity performance. Additionally, patterning-related processes [3-5] must be improved to ensure patterning fidelity when two splits are combined. The remaining challenge is to develop an intelligent approach for splitting the original layout to two different exposure mask layouts.
Generally, DPT can be categorized as two types according to its applications. One type is the so-called 'litho DPT,' which adopts dual litho-etching steps. The final pattern is a combination of two individual litho-etched patterns. In this case, a normal pattern-splitting method is required to keep the minimum HP of separate patterns as large as possible. The best method for pattern splitting is to use a rule-based approach, which separates features according to their geometrical information such as edge-to-edge and/or vertex-to-vertex distance. When using a rule-based scheme, a full-chip pattern decomposition is practical because it can has fast processing speed. The other type is 'spacer DPT,' which adopts a single split pattern as a sacrificial layer to form spacers deposited onto pattern edges. The idea implies that one can arbitrarily select one of the split layouts. However, a normal pattern-splitting technique is still required. With the assistance of polygon Boolean operations, the trim layout (to remove residual polygons) and makeup layout (to repair irregular missing polygons) can be generated using scripting electronic design automation (EDA) software.
In this study, some examples of pattern splitting are demonstrated using the Tachyon pattern-splitting tool. Furthermore, Tachyon scripts are utilized to create layouts with consideration of OPC for spacer DPT. The patterns created after each process step can be emulated with the scripts to help the process verification. All techniques developed in this study for DPT pattern splitting are applicable for 32nm node and beyond.
The optimization of the source topology and mask design [1,2] is vital to future advanced ArF technology node development. In this study, we report the comparison of an iterative optimization method versus a newly developed simultaneous source-mask optimization approach. In the iterative method, the source is first optimized based on normalized image log slopes (NILS), taking into account the ASML scanner's diffractive optical element (DOE) manufacturability constraints. Assist features (AFs) are placed under the optimized source, and then optical proximity correction (OPC) is performed using the already placed AFs, in the last step the source is re-optimized using the OPC-ed layout with the AFs. The source is then optimized using the layout from the previous stage based on a set of user specified cost function. The new approach first co-optimizes a pixelated freeform source and a continuous transmission gray tone mask based on edge placement error (EPE) based cost function. ASML scanner specific constraints are applied to the optimized source, to match ASML's current and future illuminator capabilities. Next, AF "seeds" are identified from the optimized gray tone mask, which are subsequently co-optimized with the main features to meet the process window and mask error factor requirement. The results show that the new method offers significant process window improvement.
When using the most advanced water-based immersion scanner at the 32nm node half-pitch, the image resolution will
be below the k1 limit of 0.25. If EUV technology is not ready for mass production, double patterning technology
(DPT) is one of the solutions to bridge the gap between wet ArF and EUV platforms. DPT technology implies a
patterning process with two photolithography/etching steps. As a result, the critical pitch is reduced by a factor of 2,
which means the k1 value could increase by a factor of 2. Due to the superimposition of patterns printed by two
separate patterning steps, the overlay capability, in addition to image capability, contributes to critical dimension
uniformity (CDU). The wafer throughput as well as cost is a concern because of the increased number of process
steps. Therefore, the performance of imaging, overlay, and throughput of a scanner must be improved in order to
implement DPT cost effectively. In addition, DPT requires an innovative software to evenly split the patterns into two
layers for the full chip. Although current electronic design automation (EDA) tools can split the pattern through
abundant geometry-manipulation functions, these functions, however, are insufficient. A rigorous pattern split requires
more DPT-specific functions such as tagging/grouping critical features with two colors (and hence two layers),
controlling the coloring sequence, correcting the printing error on stitching boundaries, dealing with color conflicts,
increasing the coloring accuracy, considering full-chip possibility, etc. Therefore, in this paper we cover these issues
by demonstrating a newly developed DPT pattern-split algorithm using a rule-based method. This method has one
strong advantage of achieving very fast processing speed, so a full-chip DPT pattern split is practical. After the pattern
split, all of the color conflicts are highlighted. Some of the color conflicts can be resolved by aggressive model-based
methods, while the un-resolvable conflicts, known as native conflicts, require a change in the design to achieve a DPTfriendly
design. A model-based stitching boundary correction is then used after the color conflicts are corrected.
Finally the OPC treatment is implemented on both split layouts. The OPC challenges are highlighted by examining the
printed image from both exposures. The key concepts described above with additional full chip requirements have
been successfully implemented onto Brion's Tachyo<sup>TM</sup> system. The efficiency and accuracy of the DPT pattern split
method were evaluated on a full-chip layout. The results show that the algorithm proposed in this paper is a viable
solution for the DPT pattern split.
A new framework has been developed to model 3D thick mask effects for full-chip OPC and verifications. In addition to
electromagnetic (EM) scattering effects, the new model also takes into account the non-Hopkins oblique incidence
effects commonly found in real lithography systems but missing in prior arts. Evaluations against rigorous simulations
and experimental data showed the new model provides improved accuracy, compared to both the thin-mask model and
the thick-mask model based on Hopkins treatment of oblique incidence.
To minimize or eliminate lithography errors associated with optical proximity correction, integrated circuit manufacturers need an accurate, predictive, full-chip lithography model which can account for the entire process window (PW). We have validated the predictive power of a novel focus-exposure modeling methodology with wafer data collected across the process window at multiple customer sites. Tachyon Focus-Exposure Modeling (FEM) first-principle, physics-driven simulations deliver accurate and predictive full-chip lithography modeling for producing state-of-the-art circuits.
Lithography simulation is an increasingly important part of semiconductor manufacturing due to the decreasing k1 value. It is not only required in lithography process development, but also in RET design, RET verification, and process latitude analysis, from library cells to full-chip. As the design complexity grows exponentially, pure software based simulation tools running on general-purpose computer clusters are facing increasing challenges in meeting today’s requirements for cycle time, coverage, and modeling accuracy. We have developed a new lithography simulation platform (Tachyon<sup>TM</sup>) which achieves orders of magnitude speedup as compared to traditional pure software simulation tools. The platform combines innovations in all levels of the system: algorithm, software architecture, cluster-level architecture, and proprietary acceleration hardware using application specific integrated circuits. The algorithm approach is based on image processing, fundamentally different from conventional edge-based analysis. The system achieves superior model accuracy than conventional full-chip simulation methods, owing to its ability to handle hundreds of TCC kernels, using either vector or scalar optical model, without impacting throughput. Thus first-principle aerial image simulation at the full-chip level can be carried out within minutes. We will describe the hardware, algorithms and models used in the system and demonstrate its applications of the full chip verification purposes.