Directed self-assembly (DSA) with block-copolymers (BCP) is a promising lithography extension technique to scale below 30nm pitch with 193i lithography. Continued scaling toward 20nm pitch or below will require material system improvements from PS-b-PMMA. Pattern quality for DSA features, such as line edge roughness (LER), line width roughness (LWR), size uniformity, and placement, is key to DSA manufacturability. In this work, we demonstrate finFET devices fabricated with DSA-patterned fins and compare several BCP systems for continued pitch scaling. Organic-organic high chi BCPs at 24nm and 21nm pitches show improved low to mid-frequency LER/LWR after pattern transfer.
In an ongoing study of the physical characterization of Gate-All-Around Silicon Nano Wires (GAASiNW), we found that the thin, suspended wires are prone to buckling as a function of their length and diameter. This buckling takes place between the fixed source and drain regions of the suspended wire, and can affect the device performance and therefore must be studied and controlled. For cylindrical SiNW, theory predicts that buckling has no directional preference. However, 3D CDSEM measurement results indicated that cylindrical wires prefer to buckle towards the wafer. To validate these results and to determine if the electron beam or charging is affecting our observations, we used 3D-AFM measurements to evaluate the buckling. To assure that the CDSEM and 3D-AFM measure the exact same locations, we developed a design based recipe generation approach to match the 3D-AFM and CDSEM coordinate systems. Measuring the exact same sites enables us to compare results and use 3D-AFM data to optimize CDSEM models. In this paper we will present a hybrid metrology approach to the characterization of GAASiNW for sub-nanometer variations, validating experimental results, and proposing methods to improve metrology capabilities.
A study on the optimization of etch transfer processes using 200-mm-scale production type plasma etch tools for circuit relevant patterning in the sub-30-nm pitch regime using directed self-assembly (DSA) line–space patterning is presented. This work focuses on etch stack selection and process tuning, such as plasma power, chuck temperature, and end point strategy, to improve critical dimension control, pattern fidelity, and process window. Results from DSA patterning of gate structures featuring a high-k dielectric, a metal nitride and poly Si gate electrode, and a SiN capping layer are also presented. These results further establish the viability of DSA pattern generation as a potential method for Complementary metal–oxide–semiconductor (CMOS) integrated circuit patterning beyond the 10-nm node.
Imaging of suspended silicon nanonwires (SiNW) by SEM reveals that some of the SiNW are buckled. Buckling can impact device performance and it is therefore important to characterize this phenomenon. Measuring the buckling of suspended silicon nanowires (SiNW) poses significant challenges: (1) Small dimensions - SiNW are made with diameters ranging from about 3 to 10 nm and the buckling is of a similar scale. (2) Accurate height measurements – buckling is a three dimensional phenomena.
To meet these challenges a new height map reconstruction technique was introduced, using the CDSEM side detectors signal. Measuring pixel by pixel position in X, Y and Z (height) dimensions, we can obtain the buckling vector gradient along the wire in three dimensions. In this paper we present: (1) A description of the height map reconstruction technique used. (2) Three dimensional characterization of SiNW: (a) SiNW buckling measurements (b) Characterization of buckling as a function of the SiNW length and width.
We present a study on the optimization of etch transfer processes for circuit relevant patterning in the sub 30 nm pitch regime using directed self assembly (DSA) line-space patterning. This work is focused on issues that impact the patterning of thin silicon fins and gate stack materials. Plasma power, chuck temperature and end point strategy is discussed in terms of their effect on critical dimension (CD) control and pattern fidelity. A systematic study of post-plasma etch annealing processes shows that both CD and line edge roughness (LER) in crystalline Si features can be further reduced while maintaining a suitable geometry for scaled FinFET devices. Results from DSA patterning of gate structures featuring a high-k dielectric, a metal nitride and poly Si gate electrode and a SiN capping layer are also presented. We conclude with the presentation of a strategy for realizing circuit patterns from groups of DSA patterned fins. These combined results further establish the viability of DSA pattern generation as a potential method for CMOS integrated circuit patterning beyond the 10 nm node.
We describe developments in backscattered electron (BSE) imaging in the scanning electron microscope (SEM)
beginning with the pioneering work of Von Ardenne and Knoll in Germany in the 1940's and Charles Oatley, Dennis
McMullan, Kenneth Smith and others in the 1950's. Recent work on BSE imaging with very high energy (100's of
KeV) electron beams, such as the inspection of voids in metallurgy under thick dielectrics in semiconductor
back-end-of-the-line (BEOL) structures will be presented. Finally, we will look toward the future of BSE imaging in terms of the
SEM's, detectors, and application areas.
In this paper we present physical characteristics of Silicon Nano Wires (SiNW) fabrication
processes, in line SEM metrology measurements, and a new methodology to calibrate and
correct in line roughness measurements, improving measurement accuracy.
Silicon Nano Wires (SiNW) with widths of 5 - 25 nm were characterized. Hydrogen annealing
was shown as a useful method for the fabrication of smooth suspended SiNW that are used to
build gate-all-around MOSFETs . Wires that were annealed in H2 exhibit surface roughness
below 1 nm along the full length of the 100 nm long suspended wires.
Different smoothing processes yield SiNWs with edge roughness values in the sub nanometer
range. Such small differences in roughness values, provide an interesting opportunity to evaluate
sensitivity of the SEM metrology algorithms and measurement accuracy.
A simulation program modeling SEM images including small features was developed, taking
into account the main factors that affect the SEM signal formation. Synthetic (simulated) images
of SiNW in a range of 5 - 25 nm and roughness of 0 - 1 nm were produced. Using synthetic
images with added Line Edge Roughness (LER), we characterized the performance and
sensitivity of LER algorithms and metrics. Fabricated SiNW that received various smoothing
and thinning treatments were measured with a CD-SEM. Results were compared to calibrate and
validate the experimental CD-SEM results.