The goal of the presented work is a project of a novel symmetric block encoder. The basic processing elements are cascades of reconfigurable reversible gates changing the type of gates depending on the encryption key. The presented solution proposes the use of sixteen 8-bit cascades, which configuration requires a 640-bit key. The input information is processed in five rounds. The encryption keys in the subsequent rounds differ. The design was modeled in VHDL language and placed in an FPGA chip. The project is scalable, i.e. depending on the needs, it can be modified by changing the number of gates in the cascade, the width of the information block being processed, which may result in an increase or decrease in the width of the encryption key. The number of rounds may also be modified. The large size of the encryption key should ensure the safety of the encrypted data.
The paper presents reversible circuits modelling methods in the FPGA structures. Three different methods of reconfigurable reversible gate descriptions are proposed - a direct method of output calculation and two methods of composing the gate from Fredkin and Toffoli gates. The paper shows both 4-bit and 8-bit gates. Application of developed test bench verified the correctness of our designs. The presented descriptions can be used for modelling of complex elements used e.g. in cipher machines based on quantum algorithms.