There are strong demands for techniques which are able to extend application of ArF immersion lithography.
Especially, the leading edge techniques are required to make very small hole patterns below 50nm. Several
techniques such as double patterning technique, free-form illumination and resist shrinkage technology are
considered as viable candidates. Most of all, NTD (Negative Tone Development) is being regarded as the most
promising technology for the realization of small hole patterns
When NTD process is applied, hole patterns are defined by island type features on the reticle and consequently its
optical performance shows better result compared with PTD (Positive Tone Development) process. However it is
still difficult to define extremely small hole patterns below 40nm, new combination process of NTD with RELACS
is being introduced to overcome resolution limitation. NTD combined with RELACS, which is the most advanced
lithography technology, definitely enable us to generate smaller size hole patterns on the wafer.
A chemical shrinkage technology, RELACS (Resolution Enhancement Lithography Assisted by Chemical Shrink),
utilizes the cross linking reaction catalyzed by the acid component existing in a predefined resist pattern. In case of
PTD combined with RELACS process, we already know that CD change after the shrinkage process is not
influenced by duty ratio. So we could easily reflect the RELACS bias to meet the CD target during OPC (Optical
Proximity Correction) procedure.
But NTD combined with RELACS process was not understood clearly, nor verified. It requires more investigation
of physical behavior during combined process in order to define exact hole patterns. The newly introduced process
might require additive OPC modeling procedure to satisfy target CD when NTD RELACS bias has different values
according to pitch and shape.
This study is going to include the investigation on two types of resist shrinkage process, PTD and NTD. The
optimized OPC methodology will be discussed through the evaluation on simple array hole patterns and random
Hyper NA system has been introduced to develop sub-60nm node memory devices. Especially memory
industries including DRAM and NAND Flash business have driven much finer technology to improve
productivity. Polarization at hyper NA has been well known as important optical technology to enhance
imaging performance and also achieve very low k1 process. The source polarization on dense structure has
been used as one of the major RET techniques. The process capabilities of various layers under specific
illumination and polarization have been explored.
In this study, polarization characteristic on 40nm memory device will be analyzed. Especially, TE
(Transverse Electric) polarization and linear X-Y polarization on hyper NA ArF system will be compared and
investigated. First, IPS (Intensity in Preferred State) value will be measured with PMM (Polarization
Metrology Module) to confirm polarization characteristic of each machine before simulation. Next simulation
will be done to estimate the CD variation impact of each polarization to different illumination. Third, various
line and space pattern of DRAM and Flash device will be analyzed under different polarized condition to see
the effect of polarization on CD of actual wafer. Finally, conclusion will be made for this experiment and
future work will be discussed.
In this paper, the behavior of 40nm node memory devices with two types of polarization is presented and
the guidelines for polarization control is discussed based on the patterning performances.
In resolution limited lithography process, the contact hole pattern is one of the most challenging features to be printed on wafer. A lot of lithographers struggle to make robust hole patterns under 45nm node, especially if the contact hole patterns are composed of dense array and isolated hole simultaneously. The strong OAI(Off Axis Illumination) such as dipole is very useful technique to enhance resolution for specific features. However the contact hole formed by dipole illumination usually has elliptical shape and the asymmetric feature leads to increment of chip size.
In this paper, we will explore the lithographic feasibility for the coexisting dense array with isolated contact holes and the technical issues are investigated to generate finer contact hole for both dense and isolated feature. Conventional illumination with resist shrinkage technique will be used to generate dense array and isolated contact hole maintaining original shape for the sub-50nm node memory device.