This paper compares the performance of first and second order time delay tanlock loop (TDTL) based integer frequency
synthesizers. Varying the order of the loop changes the locking region of the complete system and affects the locking
convergence. The synthesizer divider block also affects the system stability. Depending on the division factor the system
may be driven outside its locking region. This is overcome by introducing an additional block that adaptively stabilizes
the loop by driving it back to within the locking region. The results achieved indicate that the adaptive integer frequency
synthesizers operate satisfactorily. The second order loop has shown to give a better acquisition performance when
compared with the first order loop. This is due to the zero steady state phase error exhibited by the loop.
In this paper, a first order TDTL system is designed, simulated and implemented on a reconfigurable FPGA system. Initially the loop was designed and simulated using Matlab/Simulink. Subsequently some novel modifications were introduced to the TDTL in order to allow an optimized reconfigurable implementation, which eases the design process and allows for dynamic parameter and design modifications. The reconfigurable TDTL was tested in real time conditions under the same operating conditions of the simulated loop. Comparison between the simulated and real time results indicate a high degree of correlation, making the loop attractive for various practical applications.
Proc. SPIE. 5649, Smart Structures, Devices, and Systems II
KEYWORDS: Modulation, Digital filtering, Interference (communication), Field programmable gate arrays, Distortion, Frequency modulation, Fermium, Data communications, Frequency shift keying, Device simulation
In the proposed work, an adaptive first order zero-crossing digital phase locked loop (AZC-DPLL) for rapid acquisition, reliable locking, and independent of input signal level is designed, simulated and subsequently implemented on an FPGA based reconfigurable system. The finite state machine controller of the AZC-DPLL senses any changes in input signal frequency and amplitude level, that may cause the loop to loose lock, and accordingly adjusts the loop gain to bring the loop in lock within a few samples. Through this adaptation process, the conflicting requirement of fast acquisition and reliable locking is achieved.
This paper presents a study of the importance of analogue circuits testing in general and the challenges faced in testing these modules in a mixed-signal environment. It highlights the difficulties that are involved in testing analogue and mixed-signal circuits and compares them with those of testing digital only circuits. Sources of failure in integrated circuits and their relation to fault models are outlined. The paper concentrates on testing active analogue filter circuits operating in mid-range frequencies. A variety of filter circuits with different configurations and varied degrees of complexity are studied. Both soft and catastrophic single fault conditions are introduced to the circuits at the transistor, operational amplifier and feedback network levels. The work presented in the paper compares the detection of the injected faults using both frequency response and transient response voltage and current measurements. The objective is to determine the measurement method and parameter that is best at detecting a particular fault or class of faults. Analysis of the simulation data indicates that the measurement methods and parameters are complementary in terms of fault coverage and fault detection confidence.