For CMOS image sensors with pixel size under 3μm pixel, the pixel architecture in which several photodiodes share
floating diffusion and transistors tends to be adopted in order to improve full well capacity and sensitivity. In spite even
in the aforementioned advantage, adoption of the architecture may result in sensitivity imbalance between the shared
photodiodes. On reproduced images obtained by the shared pixel architecture, sensitivity imbalance between Gr and Gb
photodiodes in Bayer CFA is often conspicuous, because the imbalance results in horizontal pattern noise. We developed a low Gr/Gb sensitivity imbalance 3.2M CMOS Image Sensor with 2.2μm pixel. The pixel has the structure which is optically designed carefully in order to prevent light diffraction in pixel. According to a simulation result, read transistor gate for pixels with red color filter has an edgeless layout, because longer wave length light incident to the red pixels. For the optical design, electromagnetic analytical simulation was used because wave-optical effect cannot be ignored for the small pixel below 3μm. Gr/Gb sensitivity imbalance was measured for both the developed sensor and conventional sensor in visible light range. It was measured that the Gr/Gb sensitivity imbalance is below measurement limit.
CCD is a continuum of MOS capacitors, so its big capacitance becomes one of the major disadvantages compared with
CMOS image sensor, that cause not only large power dissipation but also other problems, such as generating an electro
magnetic interference(EMI). Single-layer electrode CCD is one of the ways to reduce CCD capacitance compared with
conventional two layer CCD electrode structure.
On the other hand, image scanning system using linear image sensor is moving from lens reduction optics system to
contact type optics system, because contact type system has smaller size than lens reduction system. Image sensor for
contact optics requires much longer CCD pitch. It means that charge transfer in CCD becomes more difficult than short
We have developed a CCD linear image sensor, called "Gratron", with gradual potential channel CCD for the purpose
of accelerating charge transfer in long channel single-layer CCD. A CCD that is driven by two phase clock is fabricated
with single layer poly Si electrodes that have wider electrode gaps and longer electrode channel length.
At the sensor that has 21um pitch pixel linear array with a single sided CCD register, high charge transfer efficiency
(>99%) is obtained at 25MHz and small capacitance of CCD is realized.
CCD is a continuum of MOS capacitors, so its big capacitance becomes one of the major disadvantages compared with CMOS image sensor, that cause not only large power dissipation but also other problems, such as generating an electro magnetic interference. We have developed a CCD linear image sensor with thin single-layer electrodes for the purpose of reducing the CCD capacitance. A two phase pulse drive CCD is fabricated with single layer poly Si electrode that has narrow electrode gaps and thinner electrode thickness. At the sensor that has 2.625um pitch 10k pixel linear array with a single sided CCD register, the coupling capacitance has been reduced to totally less than 40% compared to the conventional two layer CCD electrode structure, due to non electrode overlapping and thin thickness of the CCD electrodes. The total power consumption for CCD drive is reduced to 45% of conventional CCD and high transfer efficiency (>99%) is obtained at 20MHz. Moreover, the size of the area around CCD for the contact between electrode and clock applying wire is reduced by eliminating second layer electrode. The flatness above the silicon surface is also improved for better image quality.