Operating Characteristic (OC) curves, which are probabilities of lot acceptance as a function of fraction defective p, are
powerful tools for visualizing risks of lot acceptance errors. The authors have used OC curves for the overlay sampling
optimization, and found that there are some differences in probability of acceptance between theoretical calculation and
empirical estimation. In this paper, we derive a theoretical formulation of the probability of acceptance for several simple
cases by decomposing overlay errors, and show that the origin of the differences is the use of stratified sampling in overlay inspection.
A new overlay control method called "Polar Correction" has been developed.
In the 3x nm half-pitch generation and beyond, even in the case of using a high-end optical exposure system such as
immersion lithography with NA 1.3 over, the overlay accuracy becomes the most critical issue, and the accuracy below
10nm is indispensable . In view of the severe overlay accuracy required, the shot-to-shot intra-field overlay control
cannot be disregarded in this generation. In particular, the shot-to-shot intra-field overlay error caused by the influence of
evaporation heat has been added in the immersion exposure system. However, it is impossible to correct the shot-to-shot
intra-field overlay error by the conventional overlay control method. Therefore, we have developed the new overlay
control method called Polar Correction for higher-order intra-field error dependent on the wafer coordinates.
In this paper, we explain our new overlay control method for higher-order intra-field error, and show the simulation data
and the experimental data. We believe that Polar Correction corresponds to the generation below 10nm overlay
We have designed the lithography process for 28nm node logic devices using 1.35NA scanner. In the
28nm node, we face on the ultra-low k1 lithography in which dense pattern is affected by the mask
topography effect and the oblique-incidence. Using the rigorous lithography simulation considering
the electro-magnetic field, we have estimated accurately the feasibility of resolution of the minimum
pitch required in 28nm node. The optimum mask plate and illumination conditions have been
decided by simulation. The experimental results for 28nm node show that the minimum pitch
patterns and minimum SRAM cell are clearly resolved by single exposure.
We have developed the lithography process for 32nm node logic devices under the 1.35NA single-exposure conditions. In low-k1 generation, we have to consider the minimum pitch resolution and two-dimensional pattern fidelity at the same time. Although strong RET (Resonance Enhancement Technique) can achieve the high image contrast, it has negative effects like line end shortening and resist pattern collapse. Moderate RET such as annular illumination can combine the minimum pitch resolution and two-dimensional pattern fidelity with hyper NA illumination condition. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 110nm for contact hole pattern, respectively. The isolated contact hole needs SRAF and focus drift exposure to improve DOF. Embedded SRAM cell of 0.125&mgr;m2 area is clearly resolved across exposure and focus window.
This paper discusses the compensation method and APC system to reduce errors in mix and matching overlay between scanners. We proposed the compensation model for intra-field errors in mix and matching. And we developed the advanced APC system also to improve dynamic scan distortion using the compensation model.