Proc. SPIE. 10247, Bio-MEMS and Medical Microdevices III
KEYWORDS: Digital signal processing, Biomedical optics, Surgery, Finite impulse response filters, Signal processing, Microelectronics, System integration, Signal detection, Neurological disorders, Epilepsy, Brain mapping, Brain
This paper reports a low area, low power, integer-based digital processor for the calculation of phase synchronization between two neural signals. The processor calculates the phase-frequency content of a signal by identifying the specific time periods associated with two consecutive minima. The simplicity of this phase-frequency content identifier allows for the digital processor to utilize only basic digital blocks, such as registers, counters, adders and subtractors, without incorporating any complex multiplication and or division algorithms. In fact, the processor, fabricated in a 0.18μm CMOS process, only occupies an area of 0.0625μm2 and consumes 12.5nW from a 1.2V supply voltage when operated at 128kHz. These low-area, low-power features make the proposed processor a valuable computing element in closed loop neural prosthesis for the treatment of neural diseases, such as epilepsy, or for extracting functional connectivity maps between different recording sites in the brain.
This paper reports an integrated 64-channel neural recording sensor. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements an auto-calibration mechanism which configures the transfer characteristics of the recording site. The system has two transmission modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are released. Data streams coming from the channels are serialized by an embedded digital processor. Experimental results, including in vivo measurements, show that the power consumption of the complete system is lower than 330μW.
This paper reports a 64-channel inductively powered neural recording sensor array. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements a local auto-calibration mechanism which configures the transfer characteristics of the recording site. The system has two operation modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are transmitted. Data streams coming from the channels are serialized by an embedded digital processor and transferred to the outside by means of the same inductive link used for powering the system. Simulation results show that the power consumption of the complete system is 377uW.
This paper presents a power efficient architecture for a neural spike recording channel. The channel offers a selfcalibration
operation mode and can be used both for signal tracking (to raw digitize the acquired neural waveform) and
feature extraction (to build a PWL approximation of the spikes in order to reduce data bandwidth on the RF-link). The
neural threshold voltage is adaptively calculated during the spike detection period using basic digital operations. The
neural input signal is amplified and filtered using a LNA, reconfigurable Band-Pass Filter, followed by a fully
reconfigurable 8-bit ADC. The key element is the ADC architecture. It is a binary search data converter with a SCimplementation.
Due to its architecture, it can be programmed to work either as a PGA, S&H or ADC. In order to allow
power saving, inactive blocks are powered off depending on the selected operation mode, ADC sampling frequency is
reconfigured and bias current is dynamically adapted during the conversion. Due to the ADC low input capacitance, the
power consumption of the input LNA can be decreased and the overall power consumption of the channel is low. The
prototype was implemented using a CMOS 0.13um standard process, and it occupies 400um x 400um. Simulations from
extracted layout show very promising results. The power consumption of the complete channel for the signal tracking
operations is 2.8uW, and is increased to 3.0uW when the feature extraction operation is performed, one of the lowest
A fully differential programmable gain amplifier (PGA) with constant transfer characteristic and very low power
consumption is proposed and implemented in a 130 nm CMOS technology. The PGA features a gain range of
4 dB to 55 dB with a step size of 6 dB and a constant bandwidth of 10-550 kHz. It employs two stages of
variable amplification with an intermediate 2nd order low-pass channel filter.
The first stage is a capacitive feedback OTA using current-reuse achieving a low input noise density of
16.7 nV/√Hz. This stage sets the overall high-pass cutoff frequency to approximately 10 kHz. For all gain
settings the high-pass cutoff frequency variation is within ±5%.
The low-pass channel filter is merged with a second amplifying stage forming a Sallen-Key structure. In order
to maintain a constant transfer characteristic versus gain, the Sallen-Key feedback is taken from different taps of
the load resistance. Using this new approach, the low-pass cutoff frequency stays between 440 kHz and 590 kHz
for all gain settings (±14%). Finally, an offset cancelation loop reduces the output offset of the PGA to less than
5 mV (3σ).
The PGA occupies an area of approximately 0.06 mm2 and achieves a post-layout power consumption of
55 μW from a 1V-supply. For the maximum gain setting the integrated input referred noise is 14.4 μVRMS while
the total harmonic distortion is 0.7 % for a differential output amplitude of 0.5 V.
This paper presents a toolbox for the simulation, optimization and high-level synthesis of Nyquist-rate Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters in MATLAB. The embedded simulator uses SIMULINK C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time up to 2 orders of magnitude as compared with previous approaches - based on the use of SIMULINK elementary blocks. Moreover, S-functions are more suitable for implementing a more detailed description of the circuit. For all subcircuits, the accuracy of the behavioral models has been verified by electrical simulation using HSPICE. For synthesis purposes, the simulator is used for performance evaluation and combined with an hybrid optimizer for design parameter selection. The optimizer combines adaptive statistical optimization algorithm inspired in simulated annealing with a design-oriented formulation of the cost function. It has been integrated in the MATLAB/SIMULINK platform by using the MATLAB engine library, so that the optimization core runs in background while MATLAB acts as a computation engine. The implementation on the MATLAB platform brings numerous advantages in terms of signal processing, high flexibility for tool expansion and simulation with other electronic subsystems. Additionally, the presented toolbox comprises a friendly graphical user interface to allow the designer to browse through all steps of the simulation, synthesis and post-processing of results. In order to illustrate the capabilities of the toolbox, a 0.13μm CMOS 12-bit@80MS/s analog front-end for broadband power line communications, made up of a pipeline ADC and a current steering DAC, is synthesized and high-level sized. Different experiments show the effectiveness of the proposed methodology.
This paper presents a fast procedure for the system-level evaluation of noise and distortion in continuous-time integrated filters. The presented approach is based on Volterra’s series theory and matrix algebra manipulation. This procedure has been integrated in a constrained optimization routine to improve the dynamic range of the filter while keeping the area and power consumption at a minimum.
The proposed approach is demonstrated with the design, from system- to physical-level, of a seventh-order low-pass continuous-time elliptic filter for a high-performance broadband power-line communication receiver. The filter shows a nominal cut-off frequency of ƒc=34MHz, less than 1dB ripple in the pass-band, and a maximum stop-band rejection of 65dB. Additionally, the filter features 12dB programmable boost in the pass-band to counteract high frequency components attenuation. Taking into account its wideband transfer characteristic, the filter has been implemented using Gm-C techniques. The basic building block of its structure, the transconductor, uses a source degeneration topology with local feedback for linearity improving and shows a worst-case intermodulation distortion of -70 dB for two tones close to the passband edge, separated by 1MHz, with 70mV of amplitude.
The filter combines very low noise (peak root spectral noise density below 56nV/√Hz) and high linearity (more than 64dB of MTPR for a DMT signal of 0.5Vpp amplitude) properties. The filter has been designed in a 0.18μm CMOS technology and it is compliant with industrial operation conditions (-40 to 85°C temperature variation and ±5% power supply deviation). The filter occupies 13mm2 and exhibits a typical power consumption of 450 mW from a 1.8V voltage supply.
This paper describes the design of a 12-bit 80MS/s pipeline Analog-to-Digital converter implemented in 0.13mm CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation, synthesis and verification of Nyquist-Rate Analog-to-Digital and Digital-to-Analog Converters in MATLAB. The embedded simulator uses SIMULINK C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time and makes the proposed tool an advantageous alternative for fast exploration of requirements and as a design validation tool.
The converter is based on a 10-stage pipeline preceded by a sample/hold with bootstrapping technique. Each stage gives 1.5 effective bits, except for the first one which provides 2.5 effective bits to improve linearity. The Analog-to-Digital architecture uses redundant bits for digital correction, it is planned to be implemented without using calibration and employs a subranging pipeline look-ahead technique to increase speed. Substrate biased MOSFETs in the depletion region are used as capacitors, linearized by a series compensation.
Simulation results show that the Multi-Tone Power Ratio is higher than 56dB for several DMT test signals and the estimated Signal-to-Noise Ratio yield is supposed to be better than 62 dB from DC to Nyquist frequency. The converter dissipates less than 150mW from a 3.3V supply and occupies less than 4 mm2 die area. The results have been checked with all process corners from -40° to 85° and power supply from 3V to 3.6V.
This paper describes the design of a 12-bit 80MS/s Digital-to-Analog converter implemented in 0.13mm CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation and verification of Nyquist-Rate Analog-to-Digital and Digital-to-Analog converters in MATLAB. The embedded simulator uses SIMULINK C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time and makes the proposed tool an advantageous alternative for fast exploration of requirements and as a design validation tool.
The converter is segmented in a unary current-cell matrix for 8 MSB's and a binary-weighted array for 4 LSB's. Current sources of the converter are laid out separately from current-cell switching matrix core block and distribute in double centroid to reduce random errors and transient noise coupling. The linearity errors caused by remaining gradient errors are reduced by a modified Q2 Random-Walk switching sequence.
Simulation results show that the Spurious-Free Dynamic-Range is better than 58.5dB up to 80MS/s. The estimated Signal-to-Noise Distortion Ratio yield is 99.7% and it is supposed to be better than 58dB from DC to Nyquist frequency. Multi-Tone Power Ratio is higher 59dB for several DMT test signals. The converter dissipates less than 129mW from a 3.3V supply and occupies less than 1.7mm2 die area. The results have been checked with all process corners from -40° to 85° and power supply from 3V to 3.6V.
In this paper, we present a design approach for the high-level synthesis of programmable continuous-time Gm-C and active-RC filters with optimum trade-off among dynamic range, distortion products generation, area consumption and power dissipation, thus meeting the needs of more demanding baseband filter realizations. Further, the proposed technique guarantees that under all programming configurations, transconductors (in Gm-C filters) and resistors (in active-RC filters) as well as capacitors, are related by integer ratios in order to reduce the sensitivity to mismatch of the monolithic implementation. In order to solve the aforementioned trade-off, the filter must be properly scaled at each configuration. It means that filter node impedances must be conveniently altered so that the noise contribution of each node to the filter output be as low as possible, while avoiding that peak amplitudes at such nodes be so high as to drive active circuits into saturation. Additionally, in order to not degrade the distortion performance of the filter (in particular, if it is implemented using Gm-C techniques) node impedances can not be scaled independently from each other but restrictions must be imposed according to the principle of nonlinear cancellation. Altogether, the high-level synthesis can be seen as a constrained optimization problem where some of the variables, namely, the ratios among similar components, are restricted to discrete values. The proposed approach to accomplish optimum filter scaling under all programming configurations, relies on matrix methods for network representation, which allows an easy estimation of performance features such as dynamic range and power dissipation, as well as other network properties such as sensitivity to parameter variations and non-ideal effects of integrators blocks; and the use of a simulated annealing algorithm to explore the design space defined by the transfer and group delay specifications. It must be noted that such design space also includes most common approximation methods and network synthesis approaches as optimization variables, in order to make as widespread as possible the search for optimum solutions. The proposed methodology has been partially developed in MATLAB, taking advantage of the routines available in the signal processing and control toolboxes, and C++. The validity of the methodology and companying software will be demonstrated at the Conference and reported in the paper, using as a tailoring example the design of a programmable bank of filters for a high-performance powerline modem.