Statechart diagram and UML technique can be a vital part of early conceptual modeling. At the present time there is no much support in hardware design methodologies for reconfiguration features of reprogrammable devices. Authors try to bridge the gap between imprecise UML model and formal HDL description. The key concept in author's proposal is to describe the behavior of the digital controller by statechart diagrams and to map some parts of the behavior into reprogrammable logic by means of group of states which forms sequential automaton. The whole process is illustrated by the example with experimental results.
In the paper, the solution dedicated for FPGA devices of a synthesis of parallel multiplication systems with the alternative approach, called mutual exclusion, for results of partial products is presented. There are proposed a reducer with the factor 4:2 for parallel multipliers, based on Wallace tree structures, that are dedicated for 4-input and 1-output Look-Up Table (LUT) function generator used in FPGA devices. The elaboration refers to the solution for multiplying using FPGAs the numbers of 4 and 8 bits. However it can be enlarged up to 16 and 32 bits. The proposed solution gives the opportunity to use the probability of conditional significant partial products and faster service - fewer logic levels for special cases of multiplication related to the specific values of the sums of partial product bits.
Paper presents the CAD system, referred to as PeNCAD, which supports the design of logic controllers. The system
developed at the University of Zielona Gora allows designing concurrent logic controllers specified by means of Petri
net. The designed control system is implemented in the reprogrammable FPGA structure. The further development of
the system has been discussed in details regarding the application of the partial reconfiguration systems. The use of the
partial reconfiguration FPGA-based systems in the process of logic controllers' design enables to increase their
flexibility and functionality. Additional consequences come in the form of the decrease in hardware requirements
needed for the implementation processes of the logic controller. The reconfiguration consists in replacing of the subnet
associated with a macroplace. The Xilinx FPGA devices were used while carrying out the tests.
In this paper implementation of WWW server in SoPC (System-on-Programmable-Chip) is described. Reasons for implementing a WWW server in SoPC are explained. Moreover, the basis architecture of SoPC will be mentioned. The proposed system is divided into two parts. First part is software implemented for microprocessor, which consists of operating system, web server and additional functionalities. Second part is a control process that is implemented in FPGA structure. The software solution is based on the Nut/OS operating system and web server implemented in it. The dynamic reconfiguration is also discussed.
In the paper digital modelling and synthesis of automata in Hardware Description Languages is described. There is presented different kinds of automata and methods of realization using languages like VHDL and Verilog. Basic models for control units are: Finite State Machine (FSM), Algorithmic State Machine (ASM) and Linked State Machine (LSM). FSM, ASM and LSM can be represented graphically, which would help a designer to visualize and design in a more efficient way. On the other hand, a designer needs a fast and direct way to convert the considered designs into Hardware Description Language (HDL) codes for simulation and analysis it for synthesis and implementation.
In the paper modelling of FIR filters by means of Verilog and SystemVerilog is presented. Hardware/software co-design approach for such systems is applied in the presented design. As a final technology for a FIR filters system implementation, a FPSLIC device is considered. Filters system demonstrates example methods of communication between FPGA and AVR microcontroller in a FPSLIC structure, i.e. the communication through SRAM memory, addressing lines, data bus, interrupts. It also demonstrates how to serve peripheral elements in FPSLIC device by means of DPI interface. FIR filters model contains also interface which implements a FPSLIC cache logic and gives opportunity to a dynamical reconfiguration of FPGA in a FPSLIC structure.
In this paper, design of safety critical logic controller by means of programmable logic and microprocessor is described. The solution is based on duplicated Master-Slave architecture and results comparison from both pairs. The architecture was adapted to a FPGA device with embedded microprocessor -- in considered solution the Atmel FPSLIC was chosen. In design process tasks have been divided between hardware and software parts. The hardware part has been described in HDLs. The software for microprocessor has been written in its assembler or low-level C language. The process of verification that is based on simulation comparisons of solutions obtained in two different ways is also presented.
Hardware description languages (HDLs) allow creating bigger and bigger designs nowadays. The size of prototyped systems very often exceeds million gates. Therefore verification process of the designs takes several hours or even days. The solution for this problem can be solved by hardware acceleration of simulation.