We report on the CMOS-compatible hybrid III-V/Silicon platform developed in CEA-LETI. In order to follow the large-scale integration capabilities of silicon photonics, already available worldwide in 200mm or 300mm through different foundries, the development of CMOS-compatible process for the III-V integration is of major interest. The technological developments involve not only the hybridization on top of a mature silicon photonic front-end wafer through direct molecular bonding but the patterning of the III-V epitaxy layer, low access resistance contacts, as well as planar multilevel BEOL must also be investigated and optimized. Test vehicles for the process validation based on either distributed feedback (DFB) or distributed Bragg reflector (DBR) laser cavities were designed. A modular approach is proposed in order to minimize the impact on the already qualified silicon photonics devices. Next, a collective III–V die bonding and processing have been successfully developed in this platform. The collective bonding, based on a flexible template holder, allows for large scale die to wafer transfer in both 200 and 300mm. After the III-V substrate removal and III-V patterning relying on optimized dry etching processes, CMOS compatible metallization’s are used to realize ohmic contact on n-InP and P-InGaAs leading to contact resistivity in the range of 10−6 Ω·cm². While first demonstrations have been obtained through wafer bonding, the fabrication process was subsequently validated on III-V dies bonding with a fabrication yield of Fabry-Perot lasers of 97% in 200mm. A planarized two-metal-level BEOL was used to connect the devices, leading to a drastic reduction of series resistance between 5.5 and 7 Ω. Finally, the functionality of DFB and DBR lasers is demonstrated with SMSR up to 50 dB and maximum output power of 3 mW in CW. The overall technological features are expected improve the efficiency, density, and cost of silicon photonics PICs.
Hybrid III-V/Si laser integration on silicon photonic platform has been demonstrated several time using III-V direct bonding on top of patterned silicon [1-3]. Most of these former works have been achieved using small wafer diameter III-V fabrication line for post bonding process steps. The expected low-cost added value of silicon photonics cannot be sustained with such integration scheme. More recently, we present III-V laser integration with a CMOS compatible process using wafer to wafer bonding and 1 level of contact . In this paper, we present the technological progresses on a 200mm fully CMOS compatible hybrid III-V/Si laser technology. We introduced an improved backend of line for hybrid lasers with 2 interconnection levels, W-plugs and fully planarized process offering a state of the art access resistance and a homogeneous current density distribution over the gain material. Second, in order to optimize the use of the costly III-V material and enable the laser large scale integration on silicon we present fabrication process with die to wafer molecular bonding with high bonding yield at wafer scale. These process features will be detailed and the impact of laser performances will be presented. Finally, the scalability towards 300mm for the overall platform will be discussed.