A pair of radiation hardened high-voltage mixed signal Application Specific Integrated Circuits (ASICs) are described that provide the biasing and clocking functions required to drive large format CCDs used for space-borne cameras and focal planes. The use of these ASICs allows the CCD drive electronics to be realised in a compact and energy efficient manner saving volume, mass, and power when compared with traditional space-qualified discrete implementations. The STAR ASIC provides 24 independent voltage outputs with a 32.736V range at 10 bit resolution and with <100μV noise. Each voltage output provides a drive current of up to +/-20mA and is stable for capacitive loads of up to 10μF. An on-board telemetry system featuring a 12-bit ADC and programmable gain buffer allows internal monitoring of the output voltages plus up to 32 single ended and 4 differential external voltages, such as from PRT bridge circuits for temperature monitoring. A simple SPI serial interface provides control and telemetry read back, while all required voltages and currents are generated from internal bandgap circuits. The COMET ASIC provides 6 fully independent clock buffering channels each with individually programmable rising/falling current drive and high/low voltage levels. Output voltage levels are controlled with integrated fast response regulators that operate over a 16.368V range without the need for external decoupling capacitors. Clock drive currents can be adjusted for the load capacitance and output slew rate required over a 409.6mA range, with edge speeds <15ns achievable for small loads. Setup and control of the ASIC is also via an SPI interface with integrated safety features to ensure correct sequencing of channel operation and to prevent reverse biasing of the driver programmable voltage supplies. The COMET ASIC also features an under-voltage lock out circuit to safeguard the chip in the event of unexpected power loss. All necessary biases are generated internally and only supply decoupling, a single filtering capacitor, and a resistive divider are required to operate the device. Both devices have been designed in a commercial 0.35μm 50V tolerant HV CMOS technology using Triple Module Redundancy (TMR) and established layout techniques to harden against Total Ionising Dose (TID), Single Event Upset (SEU), and Single Event Latch-up (SEL) radiation effects. The latch-up detection circuits often needed for space electronics are therefore not required for either ASIC. Details of the architectures and circuit implementations of both ASICs will be presented. Test results from manufactured devices will be shown under representative load conditions.
Detection of the visual scene by the eye and the resultant neural interactions of the retina-brain system give us our perception of sight. We have developed an Active Pixel Sensor (APS) to be used as a tool for both furthering understanding of these interactions via experimentation with the retina and to make developments towards a realisable retinal prosthesis. The sensor consists of 469 pixels in a hexagonal array. The pixels are interconnected by a programmable neural network to mimic lateral interactions between retinal cells. Outputs from the sensor are in the form of biphasic current pulse trains suitable to stimulate retinal cells via a biocompatible array. The APS will be described with initial characterisation and test results.
A United Kingdom consortium (MI3) is founded to develop advanced CMOS image sensors for scientific applications. “Vanilla,” a 520×520 array of active pixels with 25-µm pitch is fabricated in the 0.35-µm 4M2P (4 metal, 2 poly) CMOS process and uses a 3.3-V supply. It has flushed reset circuitry to attain low reset noise and random pixel access for high-speed region-of-interest (ROI) readout. “OPIC” is a 64×72 test structure array of digital pixels with 30-µm pitch, fabricated in 0.25-µm 5M1P (5 metal 1 poly) CMOS process with a 3.3/2.5-V supply. It can perform thresholding via an in-pixel comparator for sparse readout at a high frame rate. Characterization of both sensors is performed under optical illumination and x-ray exposure. For x-ray characterization, both sensors were coupled to a structured thallium-doped cesium iodide (CsI:Tl) scintillator via a fiber optic plate. Vanilla has been found to exhibit 34±3e− read noise and a spectral response of 225±5 mA/W at 500 nm and can read a 6×6 ROI at 24,395 frames/s. OPIC has 46±3e− read noise and can perform sparse readout at up to 3700 frames/s. Based on these results, Vanilla could be employed for applications where only a small portion of the image contains relevant information, while OPIC is suited to high-speed imaging applications.
We describe our programme to develop a large-format, science-grade, monolithic CMOS active pixel sensor for future
space science missions, and in particular an extreme ultra-violet spectrograph for solar physics studies on ESA's Solar
Orbiter. Our route to EUV sensitivity relies on adapting the back-thinning and back-illumination techniques first
developed for CCD sensors. Our first large-format sensor consists of 4kx3k 5 μm pixels fabricated on a 0.25 μm CMOS
imager process. Wafer samples of these sensors have been thinned by e2v technologies with the aim of obtaining good
sensitivity at EUV wavelengths. We present results from both front and back-illuminated versions of this sensor. We also
present our plans to develop a new sensor of 2kx2k 10 μm pixels which will be fabricated on a 0.35 μm CMOS process.
In progress towards this goal, we have designed a test structure consisting of six arrays of 512x512 10 μm pixels. Each
of the arrays has been given a different pixel design to allow verification of our models and progress towards optimising
a design for minimal system readout noise and maximum dynamic range. These sensors will also be back-thinned for
characterisation at EUV wavelengths.
A UK consortium (MI3) has been founded to develop advanced CMOS pixel designs for scientific applications.
Vanilla, a 520x520 array of 25&mgr;m pixels benefits from flushed reset circuitry for low noise and random pixel access
for region of interest (ROI) readout. OPIC, a 64x72 test structure array of 30&mgr;m digital pixels has thresholding
capabilities for sparse readout at 3,700fps. Characterization is performed with both optical illumination and
x-ray exposure via a scintillator. Vanilla exhibits 34±3e<sup>-</sup> read noise, interactive quantum efficiency of 54% at
500nm and can read a 6x6 ROI at 24,395fps. OPIC has 46±3e<sup>-</sup> read noise and a wide dynamic range of 65dB
due to high full well capacity. Based on these characterization studies, Vanilla could be utilized in applications
where demands include high spectral response and high speed region of interest readout while OPIC could be
used for high speed, high dynamic range imaging.
Degenerative photoreceptor diseases, such as age-related macular degeneration and retinitis pigmentosa, are the most common causes of blindness in the western world. A potential cure is to use a microelectronic retinal prosthesis to provide electrical stimulation to the remaining healthy retinal cells. We describe a prototype CMOS Active Pixel Sensor capable of detecting a visual scene and translating it into a train of electrical pulses for stimulation of the retina. The sensor consists of a 10 x 10 array of 100 micron square pixels fabricated on a 0.35 micron CMOS process. Light incident upon each pixel is converted into output current pulse trains with a frequency related to the light intensity. These outputs are connected to a biocompatible microelectrode array for contact to the retinal cells. The flexible design allows experimentation with signal amplitudes and frequencies in order to determine the most appropriate stimulus for the retina. Neural processing in the retina can be studied by using the sensor in conjunction with a Field Programmable Gate Array (FPGA) programmed to behave as a neural network. The sensor has been integrated into a test system designed for studying retinal response. We present the most recent results obtained from this sensor.
We describe our programme to develop science-grade CMOS active pixel sensors for future space science missions, and in particular an extreme ultra-violet spectrograph for solar physics studies on the ESA Solar Orbiter. Our goal is the development of a large format 4k x 4k pixel CMOS sensor with useful sensitivity in the extreme ultra-violet (EUV) for solar physics spectroscopy and imaging. Our route to EUV sensitivity relies primarily in adapting the back-thinning and rear-illumination techniques first developed for CCD sensors; however we are also exploring the alternative approach of using a front-etch to expose the CMOS photodiodes. We have successfully back-thinned several 525 x 525 prototype CMOS sensors and proved that the devices survived the process both structurally and functionally. We have also been successful in removing the oxide from the front side of a small array of pixels, using focused ion beam etching. Preliminary results from these pixels show they are sensitive in the Ultra Violet. We have also designed a working large format 4k x 3k prototype on a 0.25 micron CMOS imager process.
We have designed two different X-ray pixel array readout Integrated Circuits for silicon pixel detectors operating between 4 keV and 25 keV. The first allows full readout of the deposited charge for each X-ray photon and is intended for imaging X-ray spectroscopy. The second is a photon counting device capable of very high rates (1 MHz per pixel) but without energy resolution. This paper compares the architectures of these two detectors and presents experimental data from complete bump-bonded devices. These detectors have many applications from X-ray diffraction to material inspection and satellite based X-ray imaging.
We have built a back-illuminated, silicon x-ray pixel detector which is bump bonded to an array of readout electronics. The system is intended for x-ray spectroscopy measurement in the 1 keV-25keV range with a resolution of 250eV FWHM. The readout electronics consists of an array of 16 by 16 preamplifiers on the bump bonded integrated circuit, this unit is wire bonded to two 128 channel integrated circuits which have signal shaping, peak-hold and sparcification logic. This paper describes the construction of the silicon detector, the readout electronics and the performance of these components. The energy range of the detector system can be increased by using a GaAs or CdZnTe detector instead of the 300 micrometers -500 micrometers thick silicon pixel detector described here.