Quantum-dot cellular automata (QCA) is an evolving technology to design circuits at nanometer levels. Most of the digital systems have an adder integrated in the circuit. Circuits in QCA are implemented using majority gates. Most of the existing adder designs are implemented using majority logic and exclusive-or logic. The circuits in QCA are prone to fabrication defects that can affect the performance of the circuit drastically. Missing cell defect is crucial among them. In this work, the existing gates used to implement the adders are analyzed, and a reliable clock zone full adder is proposed using the better fault tolerant gate. The proposed adder is more reliable since both the Sum and Carry are generated by reliable gates. Missing cell defect analysis and design validation are carried out using QCADesigner. The proposed design has fewer cells and more reliability compared to the designs which have considered reliability as an important factor to design adders.
The existing CMOS technology is facing severe challenges to keep up with the complicated needs of nanoscale devices due to several issues such as leakage current at nanoscale levels. Quantum-dot cellular automata has the ability to become an alternative to CMOS technology. In general, adder and subtractor are implemented as a single hardware, at the cost of a small reduction in the speed of addition and subtraction. A dedicated hardware for subtractor will reduce the circuit complexity and increase the speed of the operation. Four different subtractor circuit designs are proposed in quantum-dot cellular automata using different wire crossings and implementation techniques. Wire crossing count is critical in determining the cost of the circuit. The proposed multilayer crossover subtractor circuit has 12% fewer cells, 50% wire crossing reduction, and 10% area reduction compared to the existing design. The proposed rotated cell crossover subtractor circuit has 24% fewer cells, 33% clock phase reduction, 50% wire crossing reduction, and 40% area reduction compared to the existing design. Two clock zone crossover subtractor circuit designs are also proposed with smaller area and crossings. The proposed designs can be stretched to construct different N-bit subtractors. The proposed circuit designs are validated using coherence vector engine in QCADesigner.
CMOS circuits face several limitations due to the rise in leakage current at extreme nanometer levels. It has made the industry to find suitable alternatives to meet the standards set by Moore’s law. Quantum-dot cellular automata is an emerging paradigm with the potential to replace CMOS circuits at extreme nanoscale levels. Adders are integral part in almost every digital system. In this work, a novel cost-efficient full adder is proposed. The proposed full adder has the least cost, delay, and 66% reduction in the number of wire crossings, compared to existing state-of-the-art designs. The proposed design has 40% lesser cost, compared to the existing design. The proposed adder can be extended to implement any kind of N-bit adder. The proposed full adder can be implemented as a half adder without any wire crossing and additional cells. The proposed designs are evaluated and verified using QCADesigner.