Proc. SPIE. 5150, Visual Communications and Image Processing 2003
KEYWORDS: Image segmentation, Image processing, Image resolution, Field programmable gate arrays, Data communications, Image processing algorithms and systems, Sensors, Active vision, Digital cameras, Clocks
Foveal sensors can substantially increase the performance of active vision systems because of their ability to handle wide field of view and simultaneously reducing the data/bandwidth with space variant sensing. In order to process the multiresolution images and associated data structures, a new hierarchical processing has been applied to minimize data communications and retrieval. In the paper we present a hardware platform implementing a level sequential
segmentation algorithm in one of these hierarchical structures generated using a Cartesian lattice topology. This platform is designed to work at 33 frame/s using as an input the levels obtained after preprocessing the uniform resolution images from digital cameras.
The aim of this work is the test of an ASIC, intended for multiresolution images generation, with high fault coverage and low number of patterns, looking for the improvement of the results obtained with other tools. The circuit includes a embedded SRAM block used to implement several internal FIFO structures. This RAM block has been generated with the 'Memory Compiler Systems' supplied by AMS, and does not includes BIST logic, so the strategy was to generate and insert the BIST logic to completely test the RAM operation. The original test algorithm proposed by the foundry support center, has been modified for a thorough verification. Also, to achieve the controllability and observability of the shadow logic connected to the RAM outputs and inputs respectively, the necessary test logic around the embedded block has been inserted. Once the test of the RAM has been guaranteed the remaining logic needs to be tested. To accomplish this task the full scan path approach has been selected, and a hierarchical bottom-up methodology has been followed to generate the test patterns. The ATPG commercial tools ( Synopsys Test Compiler) has been used only to generate the patterns for the lowest level modules of the hierarchy tree. Making the appropriate design partitioning (basically defining the modules with registered outputs), the patterns for the upper level modules can be easily composed. Several appropriate configurations for this smart partitioning has been identified and defined. Using a simple composing technique we can obtain a considerable reduction above 37% in the number of patterns with a negligible fault coverage decrease and hardware overhead.