Differences in imaging behaviour between lithographic systems of the same wavelength result in variations of optical
proximity effects (OPE). A way to compensate these irregularities is through scanner tuning. In scanner tuning, scanner
specific adjustments are obtained through the determination of scanner knob sensitivities of relevant structures followed
by an optimization to adjust the structure CD values to be close to the desired values.
Traditionally, scanner tuning methods have relied heavily on wafer-based CD metrology to characterize both the initial
mismatch as well as the sensitivities of CDs to the scanner tuning knobs. These methods have proven very successful in
reducing the mismatch, but their deployment in manufacturing has been hampered by the metrology effort. In this paper,
we explore the possibility of using ASML's LithoTuner PatternMatcher FullChip (PMFC) computational lithography
tool to reduce the dependence on wafer CD metrology.
One tuning application using flexray illumination instead of traditional scanner knobs is presented in this work; in this
application individual critical features in wafer printing are improved without affecting other sites. The limited impact of
tuning on other structures is verified through full-chip LMC runs. Potential uses of this technology are for process
transfers from one fab to another where the OPC signature in the receiving fab is similar but not identical to the signature
of the originating fab.
The tuning application is investigated with respect to its applicability in a production environment, including further
metrology effort reduction by using scatterometry tools.
Selective Inverse Lithography (ILT) approach recently introduced by authors  has proven to be advantageous for
extending life-span of lower-NA 193nm exposure tools to achieve satisfactory 65nm contact layer patterning. We intend
to find an alternative solution without the need for higher NA tools and advanced light source optimization. In this paper
we explore possible region selection criteria for ILT application based on pitch for a full chip optical proximity
correction (OPC). Through studying the impact of a given selection criteria on runtime, resolution, and the process
window we recommend an optimal combination. With a justified choice of an ILT selection criteria, we construct a
hybrid OPC flow comprising a recursive sequence of direct assist features generation, selective ILT application, layout
repair, model OPC and hot spots screening.
With escalating costs of higher-NA exposure tools, lithography engineers are forced to evaluate life-span extension of
currently available lower-NA exposure tools. In addition to common resolution enhancement techniques such as off-axis
illumination, edge movement, or applying sub-resolution assist features, Inverse Lithography Technology (ILT) tools
available commercially at this moment offer means of extending current in-house tool resolution and enlarging process
window for random as well as periodic mask patterns. In this paper we explore ILT pattern simplification procedures and
model calibration for a range of illumination conditions. We study random pattern fidelity and critical dimension
stability across process window for 65nm contact layer, and compare silicon results for both conventional optical
proximity correction and inverse lithography techniques.
We present results for a rule based optical proximity (RB-OPC) and a model based optical proximity correction
(MB-OPC) for 0.13 μm SiGe:C BiCMOS technology. The technology provides integrated high performance
heterojunction bipolar transistors (HBTs) with cut-off frequencies up to 300 GHz. This requires an optical proximity
correction of critical layers with an excellent mask quality. This paper provides results of the MB-OPC and RB-OPC
using the Mentor Calibre software in comparison to uncorrected structures (NO-OPC). We show RB- and MB-OPC
methods for the shallow trench and gate layer, and the RB-OPC for the emitter window-, contact- and metal layers.
We will discuss the impact of the RB- and MB-OPC rules on the process margin and yield in the 0.13 μm SiGe:C
BiCMOS technology, based on CD-SEM data obtained from the evaluation of the RB- and MB-OPC corrected
The growing importance of mask simulation in a low-k1 realm is matched by an increasing need for numerical methods
capable of handling complex 3D configurations. Various approximations applied to physical parameters or boundary
conditions allowed a few methods to achieve reasonable run-times. In this work the theoretical foundation and
simulation results of an alternative 3D mask modeling method suitable for OPC simulations are presented. We have
established the throughput and accuracy of the Coupled-Dipole Simulation Method and have compared results to the
rigorous FDTD approach using a test pattern. We will discuss in detail possible approximations needed in order to
accelerate the method's performance.
Including etch-based empirical data during OPC model calibration is a desired yet controversial decision for OPC
modeling, especially for process with a large litho to etch biasing. While many OPC software tools are capable of
providing this functionality nowadays; yet few were implemented in manufacturing due to various risks considerations
such as compromises in resist and optical effects prediction, etch model accuracy or even runtime concern. Conventional
method of applying rule-based alongside resist model is popular but requires a lot of lengthy code generation to provide
a leaner OPC input. This work discusses risk factors and their considerations, together with introduction of techniques
used within Mentor Calibre VT5 etch-based modeling at sub 90nm technology node. Various strategies are discussed
with the aim of better handling of large etch bias offset without adding complexity into final OPC package. Finally,
results were presented to assess the advantages and limitations of the final method chosen.
Model-based Optical Proximity Correction (OPC) usually takes into consideration optical and resist process
proximity effects. However, the etch bias proximity effect usually can not be completely eliminated by etch process
optimization only and needs to be compensated for in OPC flow for several critical layers. Since the understanding of
the etch process effect is getting better and accurate etch bias modeling is available now, lithographers start to migrate
from rule-based correction to model-based correction. Conventionally when etch bias is considered in model-based
correction, optical/resist/etch effect is corrected in one step by using the input layout as the final etch target. In this
paper, we proposed a new flow in which etch and optical/resist process effect are separated in both model calibration and
layout correction. This double separation allows easier control over etch and resist target, resulting in drastic reduction
of OPC runtime. In addition it enables post-OPC verification at both resist and etch level. Advantages of the new
integrated model-based retarget/OPC flow in RET implementation are also discussed.
Modular OPC modeling, describing mask, optics, resist and etch processes separately is an approach to keep efforts for
OPC manageable. By exchanging single modules of a modular OPC model, a fast response to process changes during
process development is possible. At the same time efforts can be reduced, since only single modular process steps have
to be re-characterized as input for OPC modeling as the process is adjusted and optimized. Commercially available OPC
tools for full chip processing typically make use of semi-empirical models. The goal of our work is to investigate to what
extent these OPC tools can be applied for modeling of single process steps as separate modules. For an advanced gate
level process we analyze the modeling accuracy over different process conditions (focus and dose) when combining
models for each process step - optics, resist and etch - for differing single processes to a model describing the total
In the recent year tools for DFM (Design for Manufacturing) addressing the lithographic pattern transfer like LfD have
evolved besides OPC (Optical Proximity Correction) to reduce the time required from design to manufacturing along the
design to mask data preparation flow. The insertion of ORC (Optical Rule Check) after OPC in a separate mask data
preparation step has been commonly adopted in order to successfully meet the ever increasing need of an advanced
technology node like 130nm, 90nm, 65nm and below. Separate simulation runs are normally done for both OPC and
ORC and it is not unusual that different platforms (software, hardware or algorithm) are used for OPC and ORC,
especially for better ORC processing throughput. An investigation has been made to look into the possibility of a DFMlite
approach by inserting ORC into the OPC run on the same Calibre platform. This is accomplished by adding
additional intelligence necessary to provide a 'polishing' step for a hotspot identified, without increasing the combined
cycle time but having the benefit of both full OPC and partial ORC in a single simulation run.
Besides models describing the exposure tool optical system, lumped parameter resist models are the other important model used during OPC. This combination is able to deliver the speed and accuracy required during OPC. Lumped parameter resist models are created by fitting a polynomial to empirical data. The parameters of this polynomial are usually image parameters (maximum and minimum intensity, slope, curvature) taken from the optical simulation for each measured structure. During calibration of such models, it is very important to pay attention to the parameter space covered by the calibration pattern used. We analyze parameter space coverage for standard calibration patterns, real layout situation post OPC correction as well as pre OPC correction. Taking this one step further, the influence of parameter space coverage during model calibration on OPC convergence is also studied.
The latest improvements in process-aware lithography modeling have resulted in improved simulation accuracy through the dose and focus process window. This coupled with the advancements in high speed, full chip grid-based simulation provide a powerful combination for accurate process window simulation. At the 65nm node, gate CD control becomes ever more critical so understanding the amount of CD variation through the full process window is crucial. This paper will use the aforementioned simulation capability to assess the impact of process variation on ACLV (Across-Chip Linewidth Variation) and critical failures at the 65nm node. The impact of focus, exposure, and misalignment errors in manufacturing is explored to quantify both CD control and catastrophic printing failure. It is shown that there is good correlation between predicted and experimental results.
Optical & process model are used in conjunction with Mentors Calibre OPC tool to predict the behavior of a lithography process. Resist models rely exclusively on empirical measurement data, while optical models are calibrated based on the users knowledge of tool settings, but also fitting unknown parameters to empirical measurements. The final OPC model is a combination of optical & process behaviors prediction which includes resist & other process influence to meet the ever increasing demand of advanced lithography technology nodes like 90nm & below on model accuracy. Reliance of optical model creation on empirical measurement data is undoubtedly raising suspicion of how well the derived diffraction model is able to provide an accurate description of how light energy is distributed inside the resist. Various work & effort had been conducted in the past to cover defocus phenomenal on final model outcome & methodology introduced on better prediction from defocus to achieve better simulation quality, investigation has been carried out to study in further detail of existing strategy of resist & optical decoupling methodology in this work.