Scaling of designs to the 45nm and future nodes presents challenges for block level lithography. Shrinking distances
between devices drive aggressive resist placement tolerances, challenging the ability to control critical dimension (CD).
In particular, the potential variation in shallow trench isolation oxide may result in variation of resist profile and CD,
thereby affecting edge placement accuracy. Potential sources of this include wafer-to-wafer or within-wafer STI trench
depth variations, and STI CMP variations that may be induced by active area pattern density fluctuations. Some other
potential sources of CD fluctuation include oxide sidewall variation, and implant level overlay or CD errors modulating
the proximity to the oxide sidewall. Depending on the actual variation of isolation oxide and the exposure latitude of the
resist, the CD variations simply from oxide variation may consume a large portion of the CD budget.
Several examples are given of variations in resist profile and CD arising from these substrate effects. The CD
uniformity of a test structure was shown to decrease dramatically with the addition of a BARC to the resist stack, most
likely due to the suppression of substrate reflectivity variations. Simulations performed using Panoramic Technologies
software demonstrated the potential sensitivity of the factors outlined above on CD and profile errors. A comparison of
simulated vs. experimental results is made for a case of intentional overlay error, showing the failure mode of the resist
profile as the mask edge passes from STI to the active area. The simulations using a full physical model provided with
the simulation software predict a resist foot forming over the active area, which was confirmed experimentally.
Immersion lithography has emerged as the leading solution for semiconductor manufacturing for the 45nm node. With the emergence of the first full-field immersion lithography scanners, the technology is getting ready to be inserted in semiconductor manufacturing facilities throughout the world. In the initial implementation phase, the enhanced depth-of-focus provided by immersion will be utilized to mitigate the narrow process window in which leading-edge semiconductor manufacturing has been forced to operate, creating a new set of opportunities.<sup>1</sup> The area of defects, however, has remained of critical concern for this technology. It has become clear that the ultimate proof of the readiness of immersion, especially from a defect point of view, must be attained by integrating the immersion process in a production environment. In this paper, we demonstrate that fully functional 90nm PowerPC<sup>TM</sup> microprocessors have been fabricated using immersion lithography for one of the litho-critical via levels, achieving the goal of confirming that immersion lithography is a viable manufacturing solution. For this demonstration, we utilized the AT1150i (ASML), currently at Albany NanoTech (NY). The system is a 0.75 NA full-field 193nm projection (4x) scanner. We were able to achieve lithographic and overlay performance that exceeded product specifications while achieving a sufficiently low defect count so as to have yielding chips and modules. We have classified the leading types of defects that can be attributed to the immersion process and have assessed their processing impact. Electrical characterization of the integrated devices confirmed full functionality at both wafer final test (WFT) and module test (MT).
As lithographers continue to implement more exotic and complex Resolution Enhancement Techniques (RET) to push patterning further beyond the physical limits of optical lithography, full-chip brightfield inspections are be-coming increasingly valuable to help identify random and systematic defects that occur due to mask tolerance ex-cursions, OPC inaccuracies, RET design errors, or unmanufacturable layout configurations. PWQ, or Process Window Qualification, is a KLA-Tencor product* using brightfield imaging inspection technology that has been developed to address the need for rapid full-chip process window verification. PWQ is currently implemented at IBM’s 300mm facility and is being used to isolate features that repeatedly fail as a function of exposure dose and focus errors. We will demonstrate how PWQ results have assisted in: 1) qualification of reticles and new OPC models; 2) identification of non-obvious lithographic features that limit common process windows; 3) providing input for long-term design for manufacturability (DfM), OPC, and/or RET modeling. PWQ allows full or partial chips to be scanned in far less time than a multi-point common process window collected on a SEM. PWQ findings supplement these traditional analysis methods by encompassing all features on a chip, providing more detail on where the process window truly lies. Examples of marginal features that were detected by PWQ methods and their subsequent actions will be discussed in this paper for an advanced 65nm and a 90nm CMOS process.