Hemicellulose spin on carbon (SOC) material was newly developed for hardmask layer. For next generation lithography, high etching selectivity is strongly required. However, there is an issue of a balance of cost and etching selectivity in conventional process. Hemicellulose spin on carbon material is able to overcome this issue by virtue of its chemical structure and newly-developed reactive hemicellulose hardening (R2H). R2H means that hemicellulose unit is selectively hardened by chemical reaction. In this study, deep L/S and hole patterns were fabricated by using hemicellulose SOC with R2H and its dry etching selectivity was 26. Additionally, compatibility with EUV lithography was confirmed. Favorable pattern made of resist for EUV lithography was obtained on Hemicellulose SOC and successfully transferred into hemicellulose SOC.
Directed self-assembly (DSA) lithography is one of the promising next generation lithography. There are mainly 2 requirements for next generation lithography. One is smaller size lithography for logic and DRAM etc.. Another is 3D lithography for 3D semiconductor devices. Regarding DSA lithography, wide-range DSA to expand applicable patterning size was studied. However, there are not well known a potential of 3D lithography; deep pattern of directed self-assembly and deep RIE on Si devices. This paper describes xylan high-chi block copolymer and its wider range of 3D patterning size.
2. EXPERIMENTAL RESULTS AND DISCUSSION
A structure model of xylan block copolymer for wide-range DSA lithography is proposed. It is composed of A and B part in hydrophobic part and C and D part in hydrophilic part. Part D has xylan structure. The xylan block copolymers were synthesized and dissolved in PGMEA. Metal contamination was removed. Then, they were spin-coated on a substrate with guide pattern, annealed and carried out dry development using RIE on 300 mm wafer. Directed self-assembly patterns were evaluated by SEM.
In our experimental results, half pitch 8.3 nm of L/S pattern and CD 51 nm of hexagonal hole pattern were obtained. According to these results, xylan block copolymer is suitable for wide-range DSA.
Spin coated thickness of xylan block copolymer were evaluated. From 50 nm to 1.3 μm of thickness was realized and micro phase separation was confirmed. These results suggest xylan block copolymer has a possibility of wider thickness range of micro-phase separation.
Si deep RIE of xylan block copolymer was carried out. Silicon depth was 300 nm. It seems that xylan block copolymer is suitable for 3D semiconductor lithography.
It was confirmed xylan block copolymer is suitable for 3D patterning size on directed self-assembly lithography. It has a big potential for wider application of not only 2D but also 3D semiconductor devices.
Currently, there are many developments in the field of advanced lithography that are helping to move it towards increased HVM feasibility1,2,3,4. Targeted improvements in hardware design for advanced lithography are of interest to our group specifically for HVM metrics such as LWR improvement, dose reduction processes, and defect density reduction. In this work we are building on our experience to improve LWR in an advanced lithographic process by employing novel hardware solutions on our SCREEN DUO coat develop track system5 . Our approach is to implement post-litho annealing to improve resist line roughness. Although it is preferable to achieve such improvements post-etch process we feel, as many do, that post-patterning improvements are a precursor to improvements after etching6 . We hereby present our work utilizing the SCREEN DUO coat develop track system to improve aggressive dense L/S patterns.
Currently, there are many developments in the field of EUV lithography that are helping to move it towards increased HVM feasibility. Targeted improvements in hardware design for advanced lithography are of interest to our group specifically for metrics such as CD uniformity, LWR, and defect density. Of course, our work is focused on EUV process steps that are specifically affected by litho track performance, and consequently, can be improved by litho track design improvement and optimization. In this study we are building on our experience to provide continual improvement for LWR, CDU, and Defects as applied to a standard EUV process by employing novel hardware solutions on our SOKUDO DUO coat develop track system. Although it is preferable to achieve such improvements post-etch process we feel, as many do, that improvements after patterning are a precursor to improvements after etching. We hereby present our work utilizing the SOKUDO DUO coat develop track system with an ASML NXE:3300 in the IMEC (Leuven, Belgium) cleanroom environment to improve aggressive dense L/S patterns.
High chi organic lamellar-forming block copolymers were prepared with 18 nm intrinsic period Lo value. The BCPs were coated on a neutral layer on silicon substrates and were either thermally annealed or exposed to solvent vapors both in a 300mm track. The effect of lowering the glass transition temperature (Tg) on the high chi BCP was investigated. Process temperatures and times were varied. It was found that the BCP having lower Tg exhibits faster kinetics and is able to reach alignment in a shorter time than a similar BCP having higher Tg. Fingerprint defect analysis also shows that the BCP with lower Tg has lower defects. The results show that fingerprint formation can be achieved with either ether or ester type solvents depending on the BCP used. The results show that a track process for solvent annealing of high-χ BCPs is feasible and could provide the path forward for incorporation of BCP in future nodes. Finally, directed self-assembly was demonstrated by implemented high chi polymers on a graphoepitaxy test vehicles. CD and line width roughness was evaluated on patterns with a multiplication factor up to 7.
PS-b-PMMA block copolymer is a well-known DSA material, and there are many DSA patterning methods that make effective the use of such 1st generation materials. Consequently, this variety of patterning methods opens a wide array of possibilities for DSA application[1-4]. Last year, during the inaugural International DSA Symposium, researchers and lithographers concurred on common key issues for DSA patterning methods such as: defect density, LWR, placement error, etc. Defect density was specifically expressed as the biggest obstacle for new processes. Coat-Develop track systems contribute to the DSA pattern fabrication and also influence the DSA pattern performances. In this study, defectivity was investigated using an atmosphere-controlled chamber on the SOKUDO DUO track. As an initial step for expanding the DSA process window, fingerprint patterns were used for various atmospheric conditions during DSA self-assembly annealing. In this study, we will demonstrate an improved DSA process window, and then we will discuss the mechanism for this atmospheric effect.
Directed Self-Assembly (DSA) is a well-known candidate for next generation sub-15nm half-pitch lithography. [1-2] DSA processes on 300mm wafers have been demonstrated for several years, and have given a strong impression due to finer pattern results. [3-4] On t he other hand, specific issues with DSA processes have begun to be clear as a result of these recent challenges. [5-6] Pattern placement error, which means the pattern shift after DSA fabrication, is recognized as one of these typical issues. Coat-Develop Track systems contribute to the DSA pattern fabrication and also influence the DSA pattern performance. In this study, the placement error was investigated using a simple contact-hole pattern and subsequent contact-hole shrink process implemented on the SOKUDO DUO track. Thus, we will show the placement error of contact-hole shrink using a DSA process and discuss the difference between DSA and other shrink methods.
Spin coating has been used as a photoresist application method for many years,[1,2] and it has continued to include applications such as the tri-layer with stacked photoresist, Si containing anti-reflected coating (Si-ARC), and Spin on Carbon (SOC). Last year we reported EUV defectivity improvement, but the causes of some defect types were not found.[3,4] In this study, the defects unique to the coated organic film were detected using an LS9300 by Hitachi High-Technologies, and some of these defects were able to be mitigated by optimizing the SOKUDO-DUO track system. Utilizing these systems in tandem, we have revealed a mechanism of EUV pattern defect reduction linked to novel detected film coating defects. During the conference, we will discuss expansion of this concept to other film coatings.
EUV lithography (EUVL) is well known to be a strong candidate for next generation, single exposure sub-30nm halfpitch lithography. Furthermore, high-NA EUV exposure tool(s) released two years ago gave a strong impression by finer pattern results. On the other hand, it seems that the coat-develop track process remains very similar and in many aspects returns to KrF or ArF dry process fundamentals, but in practice a 26-32nm pitch patterning coat develop track process also has challenges with EUV resists. As access to EUV lithography exposures has become more readily available over the last five (5) years, several challenges and accomplishments in the track process have been reported, such as the improvement of ultra-thin film coating, CD uniformity, defectivity, line width roughness (LWR), and so on.[2-8] The coat-develop track process has evolved along with novel materials and metrology capability. Line width roughness (LWR) control and defect reduction are demonstrated utilizing the SOKUDO DUO coat-develop track system with ASML NXE:3100 and NXE:3300 exposures in the IMEC (Leuven, Belgium) cleanroom environment. Additionally, we will show the latest lithographic results obtained by novel processing approaches in the EUV coat develop track system.
Spin coating has been used as a photoresist application method for many years, and consequently certain defects have been recognized through each resist generation; i-line, KrF, ArF, ArF immersion and, most recently, EUV. Last year we reported an in-situ analysis via high-speed video camera that proved to be useful for understanding defect formation such as non-uniformity spots within organic film coatings and post-develop water-mark defects. In this study, fingerprints known as ‘tiger stripes’ around the wafer’s edge were analyzed. This phenomenon, for example, is directly related to the wafer spin-speed and air-flow during the coat-processing.
Utilizing a high-speed camera and 3D simulation, we reveal the mechanism of fingerprint generation for tiger stripe phenomena, confirm the mechanism with several different spin-speeds, and correlate these to defect inspection results. Furthermore, we will discuss the expansion to 450mmm wafers.
EUV lithography (EUVL) is well known to be a strong candidate for next generation, single exposure sub-30nm half-pitch lithography. Furthermore, a high-NA EUV exposure tool released two years ago gave a strong impression for finer pattern results. On one hand, it seems that the coat develop track process remains very similar and in many aspects returns to KrF or ArF dry process fundamentals, but in practice the 26-32nm pitch patterning coat-develop track process also has challenges with EUV resist. As access to EUV lithography exposures has become more readily available over the last five (5) years, several challenges and accomplishments in the track process have been reported, such as the improvement of ultra-thin film coating, CD uniformity, defectivity, line width roughness (LWR) and so on.[2-6] The coat-develop track process has evolved along with novel materials and metrology capability improvements. Line width roughness (LWR) and defect control are demonstrated utilizing the SOKUDO DUO coat-develop track system with an ASML NXE:3100 in the IMEC (Leuven, Belgium) clean room environment. Additionally, we will show the latest lithographic results obtained by novel processing approaches in an EUV coat-develop track system.
EUV lithography (EUVL) is well known to be a strong candidate for next generation, single exposure, sub-30nm half-pitch lithography. Much progress relevant to EUVL has been reported for a decade, however, many issues continue to challenge implementation for volume production.[1,2] On the other hand, it seems that the coat develop track process remains very similar and in many aspects returns to KrF or ArF dry process fundamentals, but in practice 26-32nm pitch patterning coat develop track process also has challenges with EUV resist. As access to EUV lithography exposures has become more readily available over the last five (5) years, several challenges and accomplishments in track processing have been reported, such as the improvement of ultra-thin film coating, CD uniformity, defectivity, line width roughness (LWR), and so on.[3,4,5,6] The coat-develop track process has evolved along with novel materials and metrology capability improvements. By coating ultra-thin under layers and resist films and by controlling resist dissolution, the SOKUDO DUO coat develop track system at IMEC (Leuven, Belgium), with ASML NXE3100 exposure, has been used to demonstrate improved CD uniformity, LWR, and defect control. Additionally, we will show the latest lithographic results obtained by novel processing approaches in EUV coat develop track system.
Typical defects to be resolved during coat-develop track processing have been confirmed during each resist generation; I-line, KrF, ArF, ArF immersion, and recently EUVV.[1-5] In this study, two types of defect formation were analyzed: organic film post coating non-uniformity spots and post develop water-marks. During substrate rotation,, a high-speed video camera is used to observe characteristic phenomena which lead to the generation of these rather typical defects. Post coating non-uniformity defects were linked to bubble formation, and post develop defects were associated with thee wafer drying conditions. By correlating high-speed camera images and defect inspection results from several different resists we can disclose the defect generation mechanism of multiple typical phenomena.
EUV lithography (EUVL) is the leading candidate for the manufacture of devices with 1× nm node and beyond.
However, many challenges remain for the industry to understand clearly and to overcome before EUVL will be ready for
application in volume production. Efforts have been made to improve the various critical components of EUVL, such as
light source, exposure tool, mask, resist material, and so on.[1,2] Among these, resist materials are considered as one of the most critical issues in realizing EUVL.[3,4] Coat-develop track system overcame several challenges for each traditional resist system (i.e. i-line, KrF ArF, and ArF immersion). EUV resist system requires ultra thin organic film coating. The under-layer thickness is below 10nm and the resist thickness is about 40nm, however, in some cases film thickness is smaller than the diameter of particles on the substrate, even if the particle size is smaller than the detection limit of defect inspection tool. Also EUV resist patterning becomes extremely small pattern pitch. It leads the difficulty of CD control because the resist solubility in develop processing depends on resist type. Some resists were significantly swelled during develop process. Swelling depends on develop time and developer materials. That behavior on EUV resist system is becoming evident. Furthermore, LWR
improvement on track processing is required. During the conference, we will discuss how to coat the substrate with ultra thin film and how to control resist dissolution to improve CD uniformity and LWR. Additionally, we will show the latest lithographic results obtained with the novel application for EUV coat-develop track system.
A baseline coat-develop track process has been established for inorganic EUV resists. Inorganic EUV resists have
already been highlighted for their higher resolution and lower Line-Width-Roughness (LWR) for lithography features as
well as strong etch resistance , , , . This inorganic resist system is not only interesting due to lithography
process capability but also do to its influences on coat-develop track processing. It is understood that this inorganic resist
system is dissolved in an aqueous solution and therefore has the different characteristics compared to typical polymer
photoresist in organic solvent.
Spin coating this aqueous resist solution leads to several challenges beyond the traditional aqueous Top Anti-Reflective
Coat (TARC) materials used decades ago. Resist spin coating systems have continuously improved over the years based
on polymer photoresists, therefore it becomes necessary to confirm if the latest coat module design and processes are
equally applicable to aqueous resists targeted for EUV lithography. Another characteristic of this inorganic system it is
not a chemical amplified resist. Post-Applied Bake (PAB), Post-Exposure Bake (PEB) and develop processes are
compared with current polymer photoresist process. In this study, a coat-develop track process baseline is established for
metrics such as film thickness uniformity, critical dimension (CD) uniformity and process defectivity. Based on this
baseline data areas for improvement in coat-develop track process are identified to enable inorganic resist transition to
volume production with EUV or E-Beam lithography.
This study reports on post-develop defect for EUV resist process. Presently, research and development of EUV resists
are continuously being carried out in terms of resolution, sensitivity, LWR. However, in the preparation of EUV
lithography for mass-production, research on the reduction of pattern defects, especially post-develop defect is also
necessary. As observed during the early stages of resist development for the various lithographic technologies, a large
number of pattern defects are commonly coming from the resist dissolution process.
As previously reported, utilizing an EUV exposure tool, we have classified several EUV specific defects on exposed and
un-exposed area. And also we have reported approaches of defect reduction.
In this work, using some types developer solution (TBAH, TBAH+, etc) comparing with current developer solution
(TMAH), EUV specific defects were evaluated. Furthermore, we investigated the defect appearing-mechanism and
approached defect reduction by track process. Finally, based on these results, the direction of defect reduction
approaches applicable for EUV resist processing was discussed.
This study reports on post develop defect on TC-less immersion resist system. There are major defects on TC-less resist
system, for example micro-Bridging, Blob and pattern collapse defect, as is well known. Among these defect, we
reported Blob and pattern collapse defect could be reduced by Acid rinse involving CO2. However, we also reported
there was the difference in the effect for each resist.
In this work, we show the great effective and slight effective case for post develop defect and we discuss the cause of
difference in acid rinse effect. We evaluated and confirmed the effect on each resist, pattern, exposed area location,
develop process and so on. Furthermore, we made a mechanism of defect appearing based on the analysis of defect
components and the measurement of resist surface condition for each develop process.
Finally we show the novel approach to post develop defect reduction on TC-less immersion resist system.
This is the study report about post-develop defect on EUV resist. The resolution, sensitivity, LWR, etc. of EUV resist
have been currently studied in the development phase. We have acknowledged that resist generates a lot of defects in its
transition from i-line, KrF, ArF and immersion-ArF. However, those were just a couple of defect types in the transition,
and they were eliminated through resist improvement.
In this study, we confirmed EUV defect type using EUV exposure tool. We also evaluate defect generation using tetrabutyl-
ammonium-hydroxide (TBAH) developer. We finally discuss on the difference of defect between using KrF and
EUV exposure tool, furthermore difference of defect between using TMAH and TBAH developer.
This study reports on blob defect reduction and process impacts by Acid Rinse System. Blob defects that appear after
develop are a common problem with i-line, KrF, ArF and ArF-immersion resists. Last year we reported Blob defects
were influenced by the develop process and were able to be decreased by improving process. Furthermore we identified
blob defects were caused from alkaline developer and could be reduced by neutralizing Acid Rinse.
In this work, we designed a novel develop process and system that reduced blob defects. We evaluated this system on
the non-topcoat immersion resist. The blob defects on immersion resist were also eliminated by this system but affected
by each resist surface condition. We also evaluated the impacts from Acid rinse for some kinds of patterns and resists,
because we needed to indentify whether there were negatively process impacts.
We reports that Acid Rinse System significantly reduced blob defect counts, and whether influenced other process
impacts. Finally we report the mechanism of the blob defects reduction.
Demand for Immersion topcoat-less resist processes is being driven by the desire to reduce the cost per wafer pass.
Two key characteristics, required by high speed immersion scanners, of topcoat-less resist are high receding contact
angle and low leaching rates. The extremely hydrophobic surface required by the scanner provides significant
challenges to the remaining processing steps, especially (developer) process related defects: pattern collapse and
hydrophobic residuals. Recent developments in materials and processing techniques have led to very promising results.
In this paper the following will be presented:
Defectivity results on 45nm L/S of several topcoat-less resists, including the effects of optimized track rinse
Results of a fundamental study on static contact angles changes of different topcoat-less resists after each
track process step to identify where in the process issues originate.
Imaging and defectivity results of 38nm L/S using the topcoat-less champion resist are presented. These
results illustrate the capability of the ASML TWINSCAN XT:1900i / Sokudo RF3i litho cluster of printing
38 nm L/S in a single exposure .
This study reports on stain defect reduction on KrF, ArF and Immersion resist system. Stain defects that appear after
develop are a common problem with i-line, KrF, ArF and ArF-immersion resists. Last year we reported a reduction of
this type of defect by optimizing the developer process. However, that optimized process used a long rinse time, and this
negatively impacts throughput.
In this work, we designed a novel develop process that reduced stain defects on the resist. Previous work showed that
stain defect formation was mainly governed by the develop process conditions. Hence, in this work we focused on
develop system improvements. On this system we identified the process both significantly reduced stain defect count
and used a shorter develop process time. In addition to reducing defect count, we identified the mechanism of reduction
of the stain defect. This was done by analyzing the composition of the defect.
In regards to stains appearing on the resist pattern after developing, this study succeeded in the reduction of these stain
defects by improving the develop process. Furthermore the mechanism of this stain defect was considered by analyzing
components of the defect.
Since the stain defects of former generation such as i-line or KrF resist defect are known well, even now this defect is
seen on the ArF resist. The appearance of this stain defect was caused by a kind of resist or pattern. Until now this defect
has been resolved by improving the resist.
In this study however, we tried to resolve the stain defect by the improvement of the developing process. As this
improvement was able to greatly reduce this defect with no change to the resist or pattern, it was understood this defect
is much influenced by the developing process. Thus it is projected the resist surface condition during the develop process
was the important key to decreasing this defect. It should be understood the number of defects was changed by the kind
of resist or pattern. First we analyzed the components of the stain defect itself. Next we analyzed the change in resist
surface condition by the new develop process.
As a result, it was realized this stain defect was from the developer chemical, it was considered that the developer
remaining on the resist film caused the stain defect. As the resist surface condition was changed by the improved
develop process, resulting in a sharp decrease in the stain defect.
In immersion lithography technique, some defects such as a watermark and a nanoscale bubble have been focused as the serious problems to be solved. In order to clarify the formation mechanism of the watermark, the in-situ observation of the drying behavior of the water drop containing the particles and without the particles, are conducted on the Si substrates. In the static watermark formation on the flat substrate, we can classify the watermark formation processes based on the watermark shapes. From the surface energy balance analysis, the particles dispersed in the DI-water adhere on the Si substrate. In addition, from the Laplace force balance, the particles adhered on the Si substrate will attract the surrounding particles. Hence, we can clarify the formation mechanism of the static watermark condensed in the ring shape. Meanwhile, in the dynamic watermark formation, we can observe clearly the condensed watermark is formed on the Si substrate and the particles move to lower region in inclined drop. In actual immersion lithography system, we can discuss the particles are more likely to remain in the immersion liquid under the lens system.
The micro bubbles condense in the concave channel and are trapped at the channel corner. In the experiments, the deionized (DI) water is dropped on a dry film resist (DFR) pattern. In the result, the micro bubble condensed and trapped at the different position in various shape patterns. The removal of micro bubbles adhered on a resist pattern has been recognized as one important factor in micro device manufacturing. We explained the condensation behavior of the micro bubble based on thermodynamics. The force acting on the bubble is estimated based on the force balance model between buoyancy and line tension. We can control and predict the micro bubble condensation by designing micro pattern arrangement.
Various sizes of concave square patterns are used for microscale bubble adhesion and removal investigation in a water/methanol mixture solution. As decreasing the surface energy of the solution, the micro bubbles are more likely to remove from the square patterns. However, the micro bubble is less likely to remove as decreasing the square size of patterns. The threshold concentration of water/methanol solution for bubble removal can be determined experimentally. Based on the surface energy analysis, the adhesion and removal mechanisms of micro bubble can be explained. The nanoscale bubbles adhered on an ArF excimer resist surface can be observed clearly by using atomic force microscope (AFM). The growth of bubbles on the ArF excimer resist surface can be imaged. By the AFM technique, nanoscale bubble can be divided into some minute bubbles on the ArF resist surface under applying certain force about 5nN. The condensation nature of nanoscale bubbles is discussed.
A short develop time process was investigated and assessed in terms of various pattern features of a resist. Process latitude for a positive DUV resist was evaluated for various pitches of line-and-space patterns and contact hole patterns for different develop times. It was found that the process latitude, depth of focus (DOF) and exposure latitude (EL) were improved by shortening develop time for various pattern features. The characteristics of CD variation to develop time for each pattern feature agree with the suggestion in our previous paper that expanding resist process latitude was strongly correlated with the resist develop rate and that terminating the develop reaction while the resist develop rate remained large was the key to expanding the process latitude. The short develop time process contributed to the larger γ characteristics of the resist, a smaller thickness loss and also a lesser degree of surface roughness in the resist pattern, which led to an appropriate resist pattern for the semiconductor process. A novel develop application system was developed by considering the loci of movements of Dainippon Screen’s (DNS) slit-scan develop nozzle and a rinse nozzle on the wafer. It was found that the novel develop application system achieved highly accurate CD controllability while realizing the benefits of the short develop time process.