This paper presents an analog front-end circuit for a 60-GHz wireless communication receiver. The feature of the
proposed analog front-end circuit is a bandwidth more than 1-GHz wide. To expand the bandwidth of a low-pass filter
and a voltage gain amplifier, a technique to reduce the parasitic capacitance of a transconductance amplifier is proposed.
Since the bandwidth is also limited by on-resistance of the ADC sampling switch, a switch separation technique for
reduction of the on-resistance is also proposed. In a high-speed ADC, the SNDR is limited by the sampling jitter. The
developed high resolution VCO auto tuning effectively reduces the jitter of PLL. The prototype is fabricated in 65nm
CMOS. The analog front-end circuit achieves over 1-GHz bandwidth and 27.2-dB SNDR with 224 mW Power