In-line Sagnac Interferometer-type optical voltage sensor for DC voltage measurement was proposed. The high input resistance of pockel’s cell contributes to the miniaturization of a sensor size and realizes highly precise measurement. The problem of DC voltage measurement was offset drift of signal processor. To solve the problem, in-line Sagnac interferometer which used in DC current sensor has been applied. Input-output characteristics and long term stability within 3 days has been confirmed. These results show that the stabilities of the optical voltage sensor are within ±0.5%.
We estimated the influence of polarization crosstalk in a Sagnac-type optical current transformer (OCT) against sensor sensitivity, and confirmed that temperature dependence of Faraday effect is canceled out by controlling the extinction ratio of transmission fiber with temperature change. Based on the above evaluation, we developed a temperature compensation element (TCE) consisting of metal-coated PM fiber. Its extinction ratio varies with temperature because of the difference between the linear expansions of metal and fiber. The ratio error of OCT using this TCE in the temperature range from -40°C to 80°C was within 0.1%, and satisfied the required accuracy for IEC 60044-8 class 0.2S.
CCD is a continuum of MOS capacitors, so its big capacitance becomes one of the major disadvantages compared with CMOS image sensor, that cause not only large power dissipation but also other problems, such as generating an electro magnetic interference. We have developed a CCD linear image sensor with thin single-layer electrodes for the purpose of reducing the CCD capacitance. A two phase pulse drive CCD is fabricated with single layer poly Si electrode that has narrow electrode gaps and thinner electrode thickness. At the sensor that has 2.625um pitch 10k pixel linear array with a single sided CCD register, the coupling capacitance has been reduced to totally less than 40% compared to the conventional two layer CCD electrode structure, due to non electrode overlapping and thin thickness of the CCD electrodes. The total power consumption for CCD drive is reduced to 45% of conventional CCD and high transfer efficiency (>99%) is obtained at 20MHz. Moreover, the size of the area around CCD for the contact between electrode and clock applying wire is reduced by eliminating second layer electrode. The flatness above the silicon surface is also improved for better image quality.