Inpria is pioneering a novel approach to EUV photoresist. Directly patternable metal oxide thin films have shown resolution better than 10nm half-pitch, with robust etch resistance, and efficient use of photons through high EUV absorbance. Inpria’s Gen2 photoresists are cast from commonly used organic coating solvents and are developed in typical negative tone develop (NTD) organic solvents. This renders them compatible with CLEAN TRACK LITHIUS Pro-EUV coater/developer system (Tokyo Electron Limited; TEL) and solvent drains. The presence of metal in the photoresist demands additional scrutiny and process development to minimize contamination risks to other tools and wafers. In this paper, we review progress in developing coat processes that reduce metal contamination levels below typical industry levels. We demonstrate minimization of trace metals contamination from wafer-to-coater/developer, and wafer-to-wafer from the spin coat process. This will also include results from surface analyses of frontside edge exclusion and backside of wafer using best-known analytical methods. In addition, we discuss results of coat uniformity and defectivity optimization. Wet clean compatibility and dry etch rate by using conventional Si-ARC/OPL etching recipe will also be presented. In conjunction with this work, we identify potential contamination pathways and means for managing contamination risk. We furthermore review equipment compatibility issues for using Inpria’s metal oxide photoresists.
In this paper we summarize our investigations into processing capability on the CLEAN TRACK<sup>TM</sup> LITHIUS Pro<sup>TM</sup> -<i>i</i> & TWINSCAN<sup>TM</sup> NXT:1950i litho cluster. Process performance with regards to critical dimension (CD) uniformity and
defectivity are investigated to confirm adherence to ITRS<sup>1</sup> roadmaps specifications. Additionally, a study of wafer
backside particle contamination is performed to understand the implications towards processing. As wafer stage chuck
cleaning on the scanner will require considerable down time, this study is necessary to understand the requirements for
Previous work from our collaboration succeeded in a processing improvement of over 80% in across wafer CD variation
by implementing the newest post exposure bake (PEB) plate design<sup>2</sup> and optimized developer process. With regards to
defectivity, the use of the advanced defect reduction (ADR) process with an optimized bevel cut of the resist allowed the
use of a high contact angle material process which is required for optimal immersion hood performance. In this work,
further optimization of the process with consideration of the design concept of the TWINSCAN<sup>TM</sup> NXT:1950i and
hardware modifications on the CLEAN TRACK<sup>TM</sup> LITHIUS Pro<sup>TM</sup> -<i>i</i> will be performed. From this investigation, it is
expected to understand the process capability of 38nm CD uniformity using novel developer hardware. Additionally, the
defectivity challenges for processing with higher scan speeds in combination with the hydrophobicity of the coating
materials and edge cut strategy will be clarified. Initial evaluation results are analyzed to understand the correlation of
various types and densities of contaminates on the backside of the wafer to the formation of wafer stage chuck focus
spots (FS). Focus spots are a localized irregular focus and leveling height.
This work is the summary of improvements in processing capability implemented and tested on the LITHIUS Pro<sup>TM</sup> -i /
TWINSCAN<sup>TM</sup> XT:1950Hi litho cluster installed at ASML's development clean room at Veldhoven, the Netherlands.
Process performance with regards to CD uniformity (CDU) and defectivity are investigated to confirm adherence to
ITRS roadmaps specifications. Specifically, imaging capabilities are tested for 40nm line 80nm pitch with the new
bake plate hardware for below hp 3Xnm generation. For defectivity, the combination of Coater/Developer defect
reduction hardware with the novel immersion hood design will be tested.
For CDU improvements, the enhanced Post Exposure Bake (PEB) plate hardware was verified versus performance of the
previous technology plate. Additionally, after the PEB improvement, a remaining across wafer signature was reduced
with an optimized develop process. The total CDU budget was analyzed and compared to previous results. Finally the
optimized process was applied to a non top coat resist process. For defectivity improvements, the effectiveness of
ASML's new immersion hood and TEL's defect reduction hardware were evaluated. The new immersion hood
performance was optimal on very hydrophobic materials, which requires optimization of the track hardware and process.
The high contact angle materials could be shown to be successfully processed by using TEL's Advanced Defect
Reduction (ADR) for residues related to the high contact angle and optimized bevel cut strategy with new bevel rinse hardware. Finally all the optimized processes were combined to obtain defect counts on a highly hydrophobic resist well within manufacturing specifications.
Through collaborative efforts ASML and TEL are continuously improving the process performance for the
LITHIUS Pro <i>-i/</i> TWINSCAN XT:1900Gi litho cluster. In previous work from this collaboration, TEL and ASML
have investigated the CDU and defectivity performance for the 45nm node with high through put processing.
CDU performance for both memory and logic illumination conditions were shown to be on target for ITRS roadmap
specifications. Additionally, it was shown that the current defect metrology is able to measure the required defect size
of 30nm with a 90% capture rate. For the target through put of 180wph, no added impact to defectivity was seen from
the multi-module processing on the LITHIUS Pro <i>-i</i>, using a topcoat resist process. For increased productivity, a new
bevel cut strategy was investigated and shown to have no adverse impact while increasing the usable wafer surface.
However, with the necessity of double patterning for at least the next technology node, more stringent requirements are
necessary to prevent, in the worst case, doubling of the critical dimension variation and defectivity.
In this work, improvements in process performance with regards to critical dimension uniformity and defectivity are
investigated to increase the customer's productivity and yield for whichever double patterning scheme is utilized.
Specifically, TEL has designed, evaluated and proven the capability of the latest technology hardware for post exposure
bake and defect reduction. For the new post exposure bake hardware, process capability data was collected for 40nm
CD targets. For defectivity reduction, a novel concept in rinse technology and processing was investigated on
hydrophobic non top coat resists processes. Additionally, improvements to reduce micro bridging were evaluated.
Finally bevel rinse hardware to prevent contamination of the immersion scanner was tested.
In order to prepare for the next generation technology manufacturing, ASML and TEL are investigating the process
manufacturability performance of the CLEAN TRACK<sup>TM</sup> LITHIUS Pro<sup>TM</sup>-<i>i</i>/ TWINSCAN<sup>TM</sup> XT:1900Gi lithocluster at
the 45nm node. Previous work from this collaboration showed the feasibility of 45nm processing using the LITHIUS<sup>TM</sup>
<i>i</i>+/TWINSCAN XT:1700i. <sup>1</sup> In this work, process performance with regards to critical dimension uniformity and
defectivity are investigated to determine the robustness for manufacturing of the litho cluster. Specifically, at the spinner
and PEB plate configuration necessary for the high volume manufacturing requirement of 180 wafers per hour, process
data is evaluated to confirm the multi-module flows can achieve the required process performance. Additionally, an
improvement in the edge cut strategy necessary to maximize the usable wafer surface without negative impact to defectivity is investigated.
In order to prepare for the next generation technology manufacturing, ASML and TEL are working together to
investigate the process performance of the LITHIUSi+/ TWINSCAN XT:1700i lithocluster through decreasing critical
dimension patterning. In this evaluation, process performance with regards to critical dimension uniformity and
defectivity are compared at different critical dimensions in order to determine areas of concentration for equipment and
process development. Specifically, design of experiments were run using immersion rinse processing at 60nm hp and
45nm hp. Defects were classified to generate a pareto for each technology node to see if there is any change in the defect
types as critical dimensions are shrinking. Similarly, critical dimension uniformity was compared through technology
nodes to see if any budget contributions have increased sensitivities to the smaller patterning features. Preliminary gauge
studies were performed for the 45nm hp evaluation, as metrology at this design rule is not yet fully proven. More work
is necessary to obtain complete understanding of metrology capabilities as this is crucial to discern precise knowledge of
processing results. While preliminary results show no adverse impact moving forward, this work is a first screening of
45nm immersion processing and more work is needed to fully characterize and optimize the process to enable robust
manufacturing at 45nm hp.
The development of next-generation exposure equipment in the field of lithography is now underway as the demand
increases for faster and more highly integrated semiconductor devices. At the same time, proposals are being made for
lithography processes that can achieve finer pattern dimensions while using existing state-of-the-art ArF exposure
Immersion exposure technology can use a high-refraction lens by filling the space between the exposed substrate and the
projection lens of the exposure equipment with a liquid having a high refractive index. At present, the development of
193-nm immersion exposure technology is proceeding at a rapid pace and approaching the realm of mass production.
However, the immersion of resist film in de-ionized water in 193-nm immersion exposure technology raises several
concerns, the most worrisome being the penetration of moisture into the resist film, the leaching of resist components
into the water, and the formation of residual moisture affecting post-processing. To mitigate the effects of directly
immersing resist in de-ionized water, the adoption of a top coat is considered to be beneficial, but the possibility is high
that the same concerns will rise even with a top coat.
It has been reported that immersion-specific defects in 193-nm immersion exposure lithography include "slimming,"
"large bridge," "swell," "micro-bridge," and "line pitch expansion," while defects generated by dry lithography can be
summarized as "residue," "substrate induced," "discoloration," and "pattern collapse." Nevertheless, there are still many
unexplained areas on the adverse effects of water seeping into a top coat or resist. It is vitally important that the
mechanisms behind this water penetration be understood to reduce the occurrence of these immersion-induced defects.
In this paper, we use top coats and resist materials used in immersion lithography to analyze the penetration and
diffusion of water. It is found that the water-blocking performance of protective-film materials used in immersion
lithography may not be sufficient at the molecular level. We discuss the diffusion of water in a top coat and its effects.
As a powerful candidate for a lithography technique that can accommodate the scaling-down of semiconductors, 193-nm immersion lithography-which realizes a high numerical aperture (NA) and uses deionized water as the medium between the lens and wafer in the exposure system-has been developing at a rapid pace and has reached the stage of practical application. In regards to defects that are a cause for concern in the case of 193-nm immersion lithography, however, many components are still unclear and many problems remain to be solved. It has been pointed out, for example, that in the case of 193-nm immersion lithography, immersion of the resist film in deionized water during exposure causes infiltration of moisture into the resist film, internal components of the resist dissolve into the deionized water, and residual water generated during exposure affects post-processing. Moreover, to prevent this influence of directly immersing the resist in de-ionized water, application of a protective film is regarded as effective. However, even if such a film is applied, it is still highly likely that the above-mentioned defects will still occur. Accordingly, to reduce these defects, it is essential to identify the typical defects occurring in 193-nm immersion lithography and to understand the condition for generation of defects by using some kinds of protective films and resist materials. Furthermore, from now onwards, with further scaling down of semiconductors, it is important to maintain a clear understanding of the relation between defect-generation conditions and critical dimensions (CD). Aiming to extract typical defects occurring in 193-nm immersion lithography, the authors carried out a comparative study with dry exposure lithography, thereby confirming several typical defects associated with immersion lithography. We then investigated the conditions for generation of defects in the case of some kinds of protective films. In addition to that, by investigating the defect-generation conditions and comparing the classification data between wet and dry exposure, we were able to determine the origin of each particular defect involved in immersion lithography. Furthermore, the comparison of CD for wet and dry processing could indicate the future defectivity levels to be expected with shrinking immersion process critical dimensions.
Utilizing de-ionized water as the medium between the wafer and lens of the exposure system and realizing high numerical aperture (NA), 193-nm immersion lithography is being developed at a great pace towards practical application. Recent improvements in materials, processing and exposure systems have dramatically reduced the defectivity levels in immersion processing. However, in order to completely eradicate immersion related defects and achieve defectivity levels required for ideal productivity, further investigation into the defect generation mechanism and full understanding of the improvements garnered so far is required. It is known that leaching of resist component materials during exposure and penetration of remaining water from the immersion scanning process are two key contributors towards immersion related defects. Additionally, the necessity to increase the hydrophobicity of the resist materials has had a signification effect on remaining resist residues. In order to more fully understand the generation of defects from the these contributions, it is necessary not only to analyze properties of the defects, but also investigate the change in composition originating from advanced processing techniques that have shown improvements in defectivity performance.
For immersion lithography at 193 nm, there is concern that the immersion of resist in water during exposure might cause water to penetrate the resist or resist components to dissolve into water, or that water remaining after exposure might affect subsequent processes. It is also thought that the same concerns are likely to be felt even if using a protective top coat. In this paper, we report on three key findings. First, after immersing resist in water using virtual immersion methods and evaluating the effect of water on critical dimension (CD) and defects, it was found that CD changes and defects increase. Second, as a result of performing the same evaluation when using a top coat, it was found that CD changes and defects increase despite top-coat application. Finally, a significant amount of knowledge can be obtained for the development of optimal 193-nm immersion lithography equipment as a result of wafer processing using real inline tools for immersion exposure and coating/developing.