With the miniaturization of devices, hot spots caused by wafer topology are becoming a problem in addition to hot spots resulting from design, mask and wafer process, and hot spot evaluation of a wide area in a chip is becoming required. Although DBM (Design Based Metrology) is an effective method for evaluating systematic defects of EUV lithography and multi-patterning, it requires a long time to evaluate because it is necessary to acquire a high-SN SEM image captured by a contour extraction for DBM that can handle low-SN SEM image captured by high-speed SEM scanning conditions.<p> </p> Contour extraction using deep learning possesses high noise immunity and excellent pattern recognition ability, and demonstrates high performance to contour extraction from low SN SEM images and multiple layers pattern ones. The proposed method is composed of annotation operation of SEM image samples, training process using annotation data and SEM image samples, and contour extraction process using the trained outcome. In the evaluation experiment, we confirmed that satisfactory contours are extracted from low SN SEM images and multiple layers pattern ones.
With the miniaturization of devices, hot spot evaluation of a wide area of a wafer for small change points such as wafer topology is required. DBM (Design Based Metrology) is an effective method for evaluating systematic defects of multiple patterning and EUV lithography. However, it takes a long time to evaluate because it is necessary to acquire a high-SN SEM image captured by low-speed SEM scanning conditions. Therefore, we developed a new pattern matching method of DBM by utilizing deep learning technology. Our proposed method can handle low-SN SEM images captured under high-speed SEM scanning conditions. <p> </p>In the proposed method, we use deep learning to estimate design layout from SEM image, and then perform pattern matching between this estimated design layout and the true design layout. The proposed method is particularly effective for pattern matching of low-SN SEM images and circuit pattern distorted during manufacturing process. It is expected that this method will be advantageous for evaluating mass systematic defects during the process development. Experimental results showed that the proposed method could estimate the design layout from the low-SN SEM image and improve the pattern matching success rate.