Plasma-induced damage to low-k dielectric materials can be quantified by separation of the effects of charged-particle
bombardment, photon bombardment, and gas-radical flux. For ion and photon bombardment, the spatial location and
extent of the damage can be determined. Damage effects from radical flux will be shown to be small. Both SiCOH and
photo-programmable low-k (PPLK) dielectrics will be discussed.
We investigate the effects of VUV and UV radiation on a number of low-k dielectric films. Two different systems
were used to investigate the effects: (1) a synchrotron radiation system as a pure VUV radiation source, and (2) an
electron-cyclotron resonance (ECR) plasma system as a plasma source (VUV plus ions). Using the
synchrotron-radiation system, we find VUV causes trapped charge accumulation within low-k dielectric films by
electron depopulation from the defect states. For organosilicate glass (SiCOH) , the defect states were located 1 eV
above the valence band of the dielectric. A model was developed to calculate in-situ charge accumulation. Trapped
charges can be depleted with UV-lamp exposure. We examined the use of different energy barriers between layers so
that less charge will be accumulated. Using the ECR plasma system, the photon effects can be separated from charged
particle effects using a capillary-array window to cover the low-k dielectric films so that only photons from plasma can
reach the dielectric. Photon fluence from the plasma can be predicted with a model and measured with a VUV
monochromator. Photons from the plasma were shown to be responsible for trapped-charge accumulation within the
dielectric, while it was found that ions bombardment results primarily on charge on the surface of the dielectrics.
As feature geometries decrease, the budgeted error for process variations decreases as well. Keeping these variations within budget is especially important in the area of gate linewidth control. Because of this, wafer-to-wafer control of gate linewidth becomes increasingly necessary. This paper shows results from 300 mm wafers with 90 nm technology that were trimmed during the gate formation process on an etch platform. After the process that opened the gate hard mask and stripped the resist, the wafers were measured using both an integrated scatterometer and a stand-alone CD-SEM. The measurements were then used to determine the appropriate amount to be trimmed by the Chemical Oxide Removal (COR) chamber that is also integrated onto the etch system. After the wafers were trimmed and etched, they were again measured on the integrated scatterometer and stand-alone CD-SEM. With the CD-SEM as the Reference Measurement System (RMS), Total Measurement Uncertainty (TMU) analysis was used to optimize the Optical Digital Profilometry (ODP) model, thus facilitating a significant reduction in gate linewidth variation. Because the measurement uncertainty of the scatterometer was reduced to a level approaching or below that of the RMS, an improvement to TMU analysis was developed. This improvement quantifies methods for determining the measurement uncertainty of the RMS under a variety of situations.