Reliability and noise tolerance represent important requirements for digital networked systems, especially in critical working conditions. These issues mostly concern the communication tasks between the network nodes, which are usually implemented on the basis of formal protocol rules. A challenging target for a reliability analysis is to provide comprehensive evaluations and acceptably accurate results. However, the current complexity of many network applications entails relevant limitations to this possibility. In this paper we present a novel system-level methodology for noise analysis of digital networked systems. In our research we have defined a simulation/analytical approach entirely based on the protocol specifications and capable to address a fast and comprehensive study of the reliability properties. The proposed methodology is illustrated through a case study on the MOST 150 protocol, which is currently used to realize multimedia networks in automotive contexts.
In the last few years the continuous demand of energy saving has brought continuous research on low-power devices, energy storage and new sources of energy. Energy harvesting is an interesting solution that captures the energy from the environment that would otherwise be wasted. This work presents an electric-mechanical model of a piezoelectric transducer in a cantilever configuration. The model has been characterized measuring the acceleration and the open circuit voltage of a piezoelectric cantilever subjected to a sinusoidal force with different values frequency and subject to an impulsive force. The model has been used to identify the optimal position in which the piezoelectric cantilever has to be placed on a shoe in order to obtain the maximum energy while walking or running. As a second step we designed the DC-DC converter with an hysteresis comparator. The circuit is able to give energy to switch on a microprocessor for the amount of time long enough to capture and store the information required. The complete system has been implemented, installed on a shoe and used in a 10 Km running competition.
In the last few years the increased development of wireless technologies led to the development of micropower devices with power management and real time power control, aimed to maximize the battery life time.1 The main and simplest method to estimate residual battery life time is by voltage measurement. This kind of measurement is simple but is useless in many cases, especially when long term Lithium-Thionyl chloride batteries are used, since its voltage is flat for more than 90% of the battery discharge. In this case, a current control should be used. However, these kinds of devices have various problems as a limited range of measurement and not negligible quiescent current that may distort the measurements. In this work we developed a micropower supervisor for wireless sensor nodes with a charge battery monitor, whose features are aimed at solving the problems just described. The current measured by a sense resistor, is filtered by a super-capacitor, amplified by a current sense amplifier and then fed to a voltage to pulse frequency modulator. In this way, the charge consumption can be estimated without the saturation of the current sense amplifier, even if the wireless node consumes time limited high current spikes, for example during transmission.
This paper presents a performance analysis of wireless image sensor networks for videosurveillance using the IEEE
802.15.4 wireless standard. The dependence of image quality and network throughput with JPEG image compression
parameters and wireless protocol parameters has been investigated. The objective of the work is to give useful guidelines
in the design of wireless videosurveillance networks over low cost, low power, low rate IEEE 802.15.4 wireless protocol.
In recent years, low distance wireless connectivity is having an exponential growth. Fast design and verification of the
performances of the wireless network is becoming a necessity for electronic industry to hit the more and more restrictive
market requests. A system level model of the network is indispensable to ensure fast and flexible design and verification.
In this work a SystemC model of the IEEE 802.15.4 standard is presented. The model has been used to verify the
performances of the 802.15.4 standard in terms of efficiency and channel throughput as a function of the number of
nodes in the network, of the dimension of the payload and of the frequency with which the nodes try to transmit.
This paper presents the definition in SystemC of wireless channels at different levels of abstraction. The different levels
of description of the wireless channel can be easily interchanged allowing the reuse of the application and baseband
layers in a high level analysis of the network or in a deep analysis of the communication between the wireless devices.
System on Chip performances in terms of speed and power dissipation are becoming dominated by communication
between the cores. The communication architectures are usually based on bus or Network on Chip. Bus-based on chip
communication architectures are simple and flexible. Network on Chip is a distributed communication architecture
allowing to overcome the bus bottleneck occurring when the number of cores connected is high. In this work we present
the integration in a SystemC NoC library of a new library for creating and simulating master and slave devices of the
AMBA AHB bus. The simulation environment has been used to evaluate the performance in terms of communication
throughput and delay in different communication architectures: AMBA AHB bus, NoC and mixed.
Systems on Chip performances in terms of speed and power dissipation is becoming dominated by communication
between the cores. To overcome the limitations of traditional bus architectures, nowadays Network-on-Chip
architectures are adopted. The Dynamic Power Management architecture and algorithm and Network-on-Chip
topology and routing algorithms should be selected considering that they both effect in a complex and complementary
way the network throughput and power dissipation. This paper presents the analysis of the effect of
Dynamic Power Management strategies on Network-on-Chip performances.
A digital controller for high frequency Switching Power Supply based on Sigma Delta modulation is proposed in this work. A technique to restrict average switching frequency in a suitable range is used. The complete system has been modelled and simulated at system level using the SystemC-WMS environment. A high precision controller
has been designed with relatively low clock frequency and area occupancy of the Sigma Delta modulator, and at the same time reducing the sensitivity to parameter statistical variations and to temperature drift.
This paper presents an implementation in SystemC of the LonTalk protocol starting from the reference code for the
MC68360 microcontroller. The SystemC code of the LonTalk protocol has been written at transaction level with the aim
of reusability and high simulation speed. The efficiency of the LonTalk protocol as been verified in a powerline network
with different number of nodes in the network, different type of traffic and in presence of noise in the channel.
We verified that SystemC can be easily used as a executable language to define protocols, ensuring reusability and
reduced design time.
Dynamic Voltage Scaling is a technique that reduces supply voltage and clock frequency, depending on system
workload, with the aim of reducing power dissipation. This works is devoted to the modelling and integration in the
same system level simulation environment of the analog DC-DC converter for Dynamic Voltage Scaling, the Dynamic
Power Management and a test System on Chip with three Masters and two Slaves connected to the AMBA AHB bus.
The DC-DC converter is described with a detail such that it is possible to verify the effect of the transient during the
change of supply voltage on the performance of the DVS algorithm. SystemC and its extension SystemC-WMS have
been used as description languages in which a system level description of the dynamic supply management coexists
with the analog switching power converter and its control.
This paper presents new dynamic voltage scaling and power management architectures for a System on Chip with an
AMBA AHB bus. The Power State Machine describing the status of the core follows the recommendations of the ACPI
standard. The algorithm controls the power states of each block on the basis of battery status, chip temperature and
The DVS and DPM architectures proposed has been described at system level in SystemC.
In particular, we investigated the possibility to change clock frequency and supply voltage for each master, slave and
bus independently when no transfer is required. A system level analysis has been performed to evaluate the effect of
different DVS and DPM algorithms, topologies and architectures on power dissipation and system performances.
In recent years, with remarkable advancements of power semiconductor devices and electronic control systems, it becomes possible to apply the induction heating technique for domestic use. In order to achieve the supply power required by these devices, high-frequency resonant inverters are used: the force commutated, half-bridge series resonant converter is well suited for induction cooking since it offers an appropriate balance between complexity and performances. Power control is a key issue to attain efficient and reliable products. This paper describes and compares four power control schemes applied to the half-bridge series resonant inverter. The pulse frequency modulation is the most common control scheme: according to this strategy, the output power is regulated by varying the switching frequency of the inverter circuit. Other considered methods, originally developed for induction heating industrial applications, are: pulse amplitude modulation, asymmetrical duty cycle and pulse density modulation which are respectively based on variation of the amplitude of the input supply voltage, on variation of the duty cycle of the switching signals and on variation of the number of switching pulses. Each description is provided with a detailed mathematical analysis; an analytical model, built to simulate the circuit topology, is implemented in the Matlab environment in order to obtain the steady-state values and waveforms of currents and voltages. For purposes of this study, switches and all reactive components are modelled as ideal and the "heating-coil/pan" system is represented by an equivalent circuit made up of a series connected resistance and inductance.
Power dissipation has become one of the main constraints during the design of complex integrated circuits in the recent years, due to the steady increasing of integration level and operating clock frequency. Power consumption is a major design issue and thus it requires the availability of effective tools for power estimation and optimization. Moreover, it is known that power analysis and optimization during the early design phases, starting from the system level, can lead to large power savings. In this paper we present Power-Kernel, an efficient object-oriented library for SystemC 2.0, which allows the easy introduction of a power model in the executable specification of a complex design.
The new generation of video coding standards (H.264/MPEG Advanced Video Codec) addresses the requirements of a network-friendly and scalable video representation, and increasing by a factor of two the compression efficiency of the current technology. The H.264 uses the SATD metric for the calculus of the prediction error.
The SATD procedure may be called about 1 million times during the visualization of a 352x288 pixel video sequence of 10 seconds. Therefore the accurate design of a dedicated hardware for the SATD is relevant in the performance of the complete codec.
This paper presents four architectures described in SystemC for the VLSI implementation of the calculus of the SATD metric. The performances of the architectures in terms of signal to noise ratio and power dissipation have been evaluated using a new SystemC library developed by the authors for the estimation of power consumption in a SystemC description of the architecture. Comparisons have been performed for different values of the number of bits of the internal representation for the four architectures. Four standard video sequences (Akiyo, Stefan, Mobile&calendar, Container) have been used to test the performance of the architectures.