The purpose of our study is to evaluate the benefit of contrast enhancement strategies on a logic metal layer at pitch 28 nm. We build up on three studies from imec and ASML . We take as a reference a Negative Tone Development (NTD) Metal Oxide Resist (MOR) process used in combination with a binary TaBN mask absorber, without SRAF, exposed with an X/Y symmetric pupil on a 0.33 NA EUV scanner, the NXE:3400 from ASML . The fading mitigation strategies leverage asymmetrical pupil (monopole), wavefront injection (Z6 aberration) and low-n attenuated Phase Shift Mask (PSM). We find very good agreement between our simulations on design clips, the theoretical expectations and the experimental data shared in the above mentioned papers on building blocks (L/S through pitch and dense tip-to-tip). Overall the three fading correction techniques are efficient to improve the printability of our use case in term of ILS. It also improves the best focus shift of L/S through pitch and between L/S and tip-to-tip. In conclusion, the most promising exposure strategy for the logic metal pitch 28 nm use case is the attenuated PSM. It provides the highest ILS, the narrower best focus range, the largest overlapping process window without any compromise on the illumination efficiency, i.e. using the full NXE:3400 throughput.
Proc. SPIE. 11609, Extreme Ultraviolet (EUV) Lithography XII
KEYWORDS: Scanners, Scanning electron microscopy, Process control, Finite element methods, Optical proximity correction, SRAF, Critical dimension metrology, Semiconducting wafers, Process modeling, OLE for process control
As technology nodes shrink, OPC model accuracy needs to the fulfill tighter requirements. Those requirements can be met only under good process control. However, OPC model accuracy relies on the specific context. Ignoring the impact of process variation on OPC accuracy could lead to break edge placement error (EPE) budget. The OPC process monitoring project at imec is conducted on imec logic N7 M2 design at pitch 32nm use case and aims at quantifying long-term validity of the OPC model in the face of NXE:3400 scanner and process variations. To account and compensate for scanner and process variations impact, the ability of restoring OPC validity by OPC model dose tuning is tested.
With the adoption of extreme ultraviolet (EUV) lithography for high volume production in the advanced wafer manufacturing fab, defects resulting from stochastic effects could be one of major yield killers and draw increasing interest from the industry. In this paper, we will present a flow, including stochastic edge placement error (SEPE) model calibration, pattern recognition and hot spot ranking from defect probability, to detect potential hot spot in the chip design. The prediction result shows a good match with the wafer inspection. HMI eP5 massive metrology and contour analysis were used to extract wafer statistical edge placement distribution data.
In this contribution we describe a simulation and experimental study investigating the impact of mask non-ideality and Mask Process Correction (MPC) model choices on Optical Proximity Correction (OPC) model accuracy for an EUV use case. We describe simulation flows and their results for two cases. In the first case we investigate the impact of using an MPC simulated mask contour vs an ideal post-OPC mask. In the second case we investigate the differences between simulations using experimentally measured and simulated mask contours. The wafer data used in this study is an N5 M2 process developed at IMEC with contour-based metrology performed using ASML MXP. NCS NDE-MPC models are created using POR CDSEM CD data and MXP contour data. OPC models are calibrated and evaluated using ASML FEM+ software.
Proc. SPIE. 10143, Extreme Ultraviolet (EUV) Lithography VIII
KEYWORDS: Oxides, Metrology, Data modeling, Calibration, Etching, Metals, Resistance, Photoresist materials, Finite element methods, Photomasks, Extreme ultraviolet, Extreme ultraviolet lithography, Optical proximity correction, Semiconducting wafers, Back end of line
Inpria has developed a directly patternable metal oxide hard-mask as a high-resolution photoresist for EUV lithography1. In this contribution, we describe a Tachyon 2D OPC full-chip model for an Inpria resist as applied to an N7 BEOL block mask application.