We describe a 2-D fully differential Readout Integrated Circuit (ROIC) designed to convert the photocurrents from an array of differential metal-semiconductor-metal (MSM) detectors into voltage signals suitable for digitization and post processing. The 2-D MSM array and CMOS ROIC are designed to function as a front-end module for an amplitude modulated/continuous time AM/CW 3-D Ladar imager under development at the Army Research Laboratory. One important aspect of our ROIC design is scalability. Within reasonable power consumption and photodetector size constraints, the ROIC architecture presented here scales up linearly without compromising complexity. The other key feature of our ROIC design is the mitigation of local oscillator coupling. In our ladar imaging application, the signal demodulation process that takes place in the MSM detectors introduces parasitic radio frequency (rf) currents that can be 4 to 5 orders of magnitude greater than the signal of interest. We present a fully-differential photodetector architecture and a circuit level solution to reduce the parasitic effect. As a proof of principle we have fabricated a 0.18 μm CMOS 32x16 fully differential ROIC with an array of 32 correlated double sampling (cds) capacitive transimpedance amplifiers (CTIAs), and a custom printed circuit board equipped to verify the test chip functionality. In this paper we discuss the fully differential IC design architecture and implementation and present the future testing strategy.
An alternative, class AB configuration of a proven class A readout cell for active/passive imaging systems is presented. Comparison between the two approaches shows that class AB circuit lowers power consumption and reduces noise by a factor of 3 while using nearly equal chip area. On the other hand, class AB has lower bandwidth because it operates at lower bias currents. A 0.5μm CMOS test chip that includes both types of readout circuits has been designed, fabricated and is currently being tested. Simulation results, using readout circuits from this test chip, are used to compare the two configurations.