A 1-D CMOS digital pixel image sensor system architecture is presented. Each pixel contains a photodiode, a low-power
charge-sensitive amplifier, low noise sample/hold circuit, an 8-bit single-slope ADC, a 12-bit shift register and timing &
control logic. The pixel is laid out on a 4µm pitch to enable a cost efficient implementation of high-resolution pixel
arrays. Fixed pattern noise (FPN) is reduced by a charge-sensitive feedback amplifier, and the reset noise is cancelled by
correlated double sampling read out. A prototype chip containing 512 pixels has been fabricated in the TSMC .25um
logic process. A 40μV/e- conversion gain is measured with 100 e- rms read noise.