Recent advances in lithography simulation have made full-chip lithography rule checking (LRC) practical and even mandatory for many fabs, especially those operating with half-pitches under 100nm. These LRCs routinely identify marginal or even fatal manufacturability problems (hot-spots), especially when simulated through process corners. Until recently, when hot-spots were identified, the only options were to reject the tapeout for additional layout modifications, re-run OPC with a different recipe, or use a DRC-tool to do "blind" cut-and-paste repairs under the assumption that making fatal errors non-fatal is sufficient to make them "good." Using a commercial LRC tool, we will inspect OPC data on a production design to identify a typical volume of real and potential hot-spots. Next, using Halo-Fix from Aprio Technologies, we will apply local repairs, choosing rule-based or model-based repair strategies as appropriate for each type of hot-spot. Using this method, "intelligent" changes in the hot-spot areas can be made which accurately account for lithography interactions and process variations, in order to optimize for manufacturing robustness. To verify that the repairs are acceptable, LRCs will be performed and the results analyzed.
Design tools exploit design hierarchy for speed, efficiency and reuse. Conventional optical proximity correction (OPC) tools process design layouts in a sequential mode layer by layer to ensure stability of the resolution enhancement technology (RET) corrections. A typical sub-100 nm design layout is very large and OPC expands the data volume significantly. The large data volumes and long run-times associated with conventional OPC are becoming critical bottlenecks for manufacturing turn-around time.
In a full-chip layout comprised of a library of cells, a cell may be instantiated thousands of times. Aprio's incremental OPC technology applies a design-like methodology that exploits the hierarchical structure of the layout. OPC is applied once per master cell rather than once per cell placement. The master cells are reused and can be instantiated across different designs. These pre-OPC'ed cells are reconverged or "stitched" together at their interacting halo areas to build up proximity-corrected, hierarchical layouts. This alleviates the need to run OPC sequentially on multiple designs where the master cell is instantiated, thus leading to significantly reduced run-time and data size. We are able to extend this to applications such as manufacturing engineering change order (ECO) handling and design re- spins without the need to rerun the entire OPC layout. Since our incremental technology can "stitch" together previously OPC corrected areas and cells, we are able to combine less complex areas along with "critical-care" areas leading to a more robust final layout that is optimally designed for manufacturing.
Optical proximity corrections (OPC) applied to design layouts are targeted for the nominal process condition FoEo that maintains manufacturing throughput and yield. For designs at 130 nm and above, this is usually sufficient to provide the needed resolution enhancement technology (RET) corrections for high-yield manufacturing. However, for sub-100 nm designs, lack of feature fidelity across the process window becomes a significant contributor to yield loss. It becomes critical to simulate across the lithography process window to predict feature behavior over a wide range of focus and exposure (FE) conditions. KLA-Tencor's DesignScan tool simulates the performance of a design across the process window and detects any defects which are then flagged for repair.
In the conventional OPC flow, correction of defects entails changing the OPC recipe and redecorating the entire layout. Aprio's reconfigurable OPC technology allows one to compute more aggressive OPC corrections at the error locations. This reconfigured OPC replaces the original corrections only at the error locations. This allows prior OPC results to be re-used. The halo or boundary areas associated with the stitching of the modified OPC are simulated and verified and the results are converged back into the layout. This allows the designer to start with a nominal OPC design and by applying reconfigurable OPC technology, eliminate printability errors in the process window, expand the process window, resulting in more robust design performance across the process window. This mask design inspection and optimization method improves yield and shortens cycle time to first wafers, thus providing closure for the design to manufacturing loop.