The 22nm logic technology node with dimensions of ~32nm will be the first node to require some form of pitch-halving.
A unique combination of a Producer APF(R)-based process sequence and GDR-based design style permits
implementation of random logic functions with regular layout patterns. The APF (Advanced Patterning Film) pitch-halving
approach is a classic Self-Aligned Double Patterning scheme (SADP) [1,2,3,4] which involves the creation of
CVD dielectric spacers on an APF sacrificial template and using the spacers as a hardmask for line frequency doubling.
The Tela CanvaTM implements Gridded Design Rules (GDR) using straight lines placed on a regular grid. Logic
functions can be implemented using lines on a half-pitch with gaps at selected locations.
The capability and performance of the production-proven DUV ALTA 4300 system has been extended by the development of two new optical subsystems: a 0.9 NA, 42X reduction lens and a high-bandwidth acousto-optic deflector based beam position and intensity correction servo. The PSM overlay performance has been improved by modifications to the software algorithms. The enhanced performance, delivered by these subsystem improvements, has been introduced as a new product-the ALTA 4700. Characterization data show improved resolution performance in line end shortening, through pitch CD bias and feature corner acuity. The AOD subsystem reduces stripe beam placement errors and random and systematic beam intensity errors. This has enabled local CD uniformity to be reduced to 4.3 nm (3σ) and global CD uniformity to be reduced to 6 nm (3σ). Second layer overlay performance is now 20 nm (max error). This paper also demonstrates superior X-Architecture performance delivered by the ALTA 4700. Characterization data show global CD uniformity in 0°, 45°, 90°, and 135° orientations better than 6.5nm (3σ); mean CD control in all 4
orientations less than 3.6nm; and smooth angled lines through a wide range of angles. A split lot wafer evaluation demonstrates the equivalence of wafers produced DUV ALTA system reticles vs. those produced with reticles from a 50kV electron beam system. The evaluation shows the interchangeability of these two systems for 90nm Metal 1 applications-with no changes to the wafer OPC (originally optimized for the 50kV system). Characterization data focus on final wafer electrical performance-the performance characteristic that determines ultimate integrated circuit device yield.
Ramping an integrated circuit from first silicon bring-up to production yield levels is a challenge for all semiconductor products on the path to profitable market entry. Two approaches to accelerating yield ramp are presented. The first is the use of laser mask writers for fast throughput, high yield, and cost effective pattern transfer. The second is the use of electrical test to find a defect and identify the physical region to probe in failure analysis that is most likely to uncover the root cause. This provides feedback to the design team on modifications to make to the design to avoid the yield issue in a future tape-out revision. Additionally, the process parameter responsible for the root cause of the defect is forward annotated through the design, mask and wafer coordinate systems so it can be monitored in-line on subsequent lots of the manufacturing run. This results in an improved recipe for the manufacturing equipment to potentially prevent the recurrence of the defect and raise yield levels on the following material. The test diagnostics approach is enabled by the seamless traceability of a feature across the design, photomask and wafer, made possible by a common data model for design, mask pattern generation and wafer fabrication.
In this paper, we discuss the results from a test chip that demonstrate the manufacturability and integration-worthiness of the X Architecture at the 90-nm technology node. We discuss how a collaborative effort between the design and chip making communities used the current generation of mask, lithography, wafer processing, inspection and metrology equipment to create 45 degree wires in typical metal pitches for the upper layers on a 90-nm device in a production environment. Cadence Design Systems created the test structure design and chip validation tools for the project. Canon’s KrF ES3 and ArF AS2 scanners were used for the lithography. Applied Materials used its interconnect fabrication technologies to produce the multilayer copper, low-k interconnect on 300-mm wafers. The results were confirmed for critical dimension and defect levels using Applied Materials’ wafer inspection and metrology systems.
The X Architecture is a new way of orienting the interconnect on an integrated circuit using diagonal pathways, as well as the traditional right-angle, or Manhattan, configuration. By enabling designs with significantly less wire and fewer vias, the X Architecture can provide substantial improvements in chip performance, power consumption and cost. Members of the X Initiative semiconductor supply chain consortium have demonstrated the production worthiness of the X Architecture at the 130-nm and 90-nm process technology nodes. This paper presents an assessment of the manufacturing readiness of the X Architecture for the 65-nm technology node. The extent to which current production capabilities in mask writing, lithography, wafer processing, inspection and metrology can be used is discussed using the results from a 65-nm test chip. The project was a collaborative effort amongst a number of companies in the IC fabrication supply chain. Applied Materials fabricated the 65-nm X Architecture test chip at its Maydan Technology Center and leveraged the technology of other X Initiative members. Cadence Design Systems provided the test structure design and chip validation tools, Dai Nippon Printing produced the masks and Canon’s imaging system was employed for the photolithography.