We have developed a high resolution amorphous selenium (a-Se) direct detection imager using a large-area compatible back-end fabrication process on top of a CMOS active pixel sensor having 25 micron pixel pitch. Integration of a-Se with CMOS technology requires overcoming CMOS/a-Se interfacial strain, which initiates nucleation of crystalline selenium and results in high detector dark currents. A CMOS-compatible polyimide buffer layer was used to planarize the backplane and provide a low stress and thermally stable surface for a-Se. The buffer layer inhibits crystallization and provides detector stability that is not only a performance factor but also critical for favorable long term cost-benefit considerations in the application of CMOS digital x-ray imagers in medical practice. The detector structure is comprised of a polyimide (PI) buffer layer, the a-Se layer, and a gold (Au) top electrode. The PI layer is applied by spin-coating and is patterned using dry etching to open the backplane bond pads for wire bonding. Thermal evaporation is used to deposit the a-Se and Au layers, and the detector is operated in hole collection mode (i.e. a positive bias on the Au top electrode). High resolution a-Se diagnostic systems typically use 70 to 100 μm pixel pitch and have a pre-sampling modulation transfer function (MTF) that is significantly limited by the pixel aperture. Our results confirm that, for a densely integrated 25 μm pixel pitch CMOS array, the MTF approaches the fundamental material limit, i.e. where the MTF begins to be limited by the a-Se material properties and not the pixel aperture. Preliminary images demonstrating high spatial resolution have been obtained from a frst prototype imager.
An ultra-high definition experimental camera system has been designed with double the horizontal and vertical resolution of HDTV. An 8M-pixel CCD with a progressive 60 frame-per- second scan-rate has been developed for the system. The 34 mm X 17.2 mm image area has 4046 (H) X 2048 (V) active imaging pixels with 8.4-micrometers squares. This CCD has a split- frame transfer structure and sixteen 37.125 MHz outputs so that the vertical and horizontal transfer frequencies are almost the same as those of HDTV. The split-frame transfer structure halves the required VCCD clock speeds and thus improves charge transfer efficiency. The multiple-output structure with its 16 outputs enables high data-rate imaging for ultra-high resolution moving pictures. In the signal processing section, analog gain adjustment circuits correct for the mismatches in the characteristics of outputs, and a correlated double-sampling technology is employed on each of the 16 CCD output signals. The output signals are digitized by 12-bit ADCs. The converted signals are then sent to the digital signal processing (DSP) circuits. In the DSP circuits, the upper half of the captured image is vertically inverted. All of the output data is then merged into a 4K X 2K pixel image and reformatted to create twenty-four 640 (H) X 480 (V) pixel sub-images for image processing. After contour compensation processing, the video signals are converted into an analog signal and presented on two ultra high resolution video monitors.
This paper presents the development status of a 50-million pixel, large-format, electro-optical framing charge-coupled device (CCD) with on-chip graded forward motion compensation. The development addresses the requirements set forth by the US Naval Research Lab for Ultra-high Resolution reconnaissance. A 5,040 by 10,080 element CCD has been developed and demonstrated to meet the 100-Mpixel/s UHR requirement.
CCD devices fabricated on low-resistivity silicon epi (30 - 60 (Omega) -cm) exhibit satisfactory imaging characteristics in the visible spectrum but inferior imaging characteristics in the near infrared and x ray regions. This is a result of the greater penetration depth of the photons, which tend to travel beyond the depletion regions under the CCD gates causing optical crosstalk and poor responsivity. This represents a performance limiting issue for acousto-optical applications and scientific imaging. CCD devices fabricated on high-resistivity silicon epi (>= 1000 (Omega) -cm) with increased epi layer thickness will exhibit superior imaging performance for near-infrared and x-ray photons. This is because the width of the depletion regions is much greater compared to devices on conventional substrates. DALSA has fabricated CCD structures on high-resistivity substrates and has examined their performance, in particular imaging behavior in the near-infrared region of the spectrum. We also examine the behavior of the nonimaging circuitry associated with the CCD such as the output amplifiers.
The applicability of large-area full-frame CCD image sensor technology to large optical format aerial reconnaissance applications has been recently demonstrated. The requirements of low-contrast, high-resolution imaging at high frame rates have generated the need for a manufacturable, multitap, small-pitch, wafer-scale CCD image sensor technology. The added requirement of incorporation of electronic motion compensation at the focal plane has generated the need for multisegmented full-frame area array architectures. Characterization results from the newly developed 5040 X 5040 element, eight-tap, full-frame image sensor with multisegmentation for electronic motion compensation are discussed. Experimental determination of resistive-capacitive time constants for metal strapped vertical clock busses on wafer-scale sensors is discussed.
Focal planes constructed of high speed, high resolution CCD image sensors are suitable for airborne reconnaissance applications, but have mainly consisted of linear and TDI array configurations. Until recently large format area arrays have been limited to staring applications, characterized by long integration times and slow readout rates. Large area reconnaissance focal planes require opto-mechanical systems for motion compensation across the imaging plane. A unique CCD architecture has been developed to provide electronic image motion compensation using variable speed vertical clocking segments. This architecture has been applied to very large full frame CCD sensors having 2048 X 2048 and 5040 X 5040 pixel formats.
Reconnaissance systems incorporating solid-state image sensors have advantages over film- based systems in their ability to provide real-time images and transmit digital data to a remote location. In this application area array sensors have advantages over linear and TDI type sensors in eliminating the need for the aircraft to travel in a straight line as is required for 'push broom' imaging. DALSA has previously developed a single output 2048 X 2048 area array which evolved to a four output high speed image sensor suitable for airborne reconnaissance. In this paper we discuss a four output 5120 X 5120 image sensor; this sensor is a prototype for an 8 output imager suitable to replace film recording media for airborne reconnaissance. We review the performance of the existing 5120 X 5120 array and discuss the design modifications implemented on the second generation device to match reconnaissance requirements, improve performance and enhance yield.
A 26.2 million pixel CCD Imager Sensor has been successfully designed and fabricated. The device uses a full frame architecture with 5,120 X 5,120 pixels organization. With a pitch of 12 microns in both dimensions, the overall image zone is 61.44 mm X 61.44 mm. The charge storage capacity of each photosite is greater than 130,000 electrons and the minimum detectable charge is 50 electrons when correlated double sampling is used. The device is also capable of reduced dark current operation of 60 pA/cm<SUP>2</SUP> when operated in the surface inversion mode. The device has four outputs, each of which can operate up to 12 MHz.