A monolithically integrated optical receiver in 0.6 μm bipolar complementary metal oxide semiconductor (BiCMOS) technology with 45 channels, each working at a data rate of 3.125 Gbit/s, is described. The optical receiver uses integrated pin photodiodes with a diameter of 90 μm. This parallel optical silicon receiver is capable of operating at 100°C. The parallel optical receiver consumes less than 950 mW in total and each of its channels achieve an optical sensitivity of −17.5 dBm at 850 nm wavelength and a bit error ratio of 10−9.
We present a chip, which is suited for applications in data-communication areas as well as in image-processing applications. Through the combination of parallel signal gathering and processing, we save components and we can increase the processing rate. We think thereby on problems like pre processing in camera systems also called "intelligent sensor". The chip has a structure as follows. Every processor element contains an optical detector, a trans-impedance amplifier and a comparator. A digital logic is directly connected to these components. This logic realizes the programmable processing of the signals. Each processor element is connected to its four direct orthogonal neighbours within the processor array. The digital parts consist of a special processor. It realises simple hard-wired image algorithms. As an example for cooperation of the analogue and digital part we have implemented some morphologic operations. Our receiver consists of a 8×8 photodiode array. A data rate of 625 Mbit/s for an average optical power in the range of 25 µW to 500 µW is possible for a bit-error-rate of 10-9 per channel. Signal processing limits the frequency to 200 MHz for a processor element according to simulations. Using an image with a size of 6×6 according to parallel data transfer a data throughput of 7.2 GHz results.
In resent publications we presented PIN photodiodes with a bandwidth of 600MHz implemented in low-cost 0.6μm BiCMOS technology. A new method to increase the response time of these PIN photodiodes is proposed here. This method was applied to design an optical fiber receiver with a maximum possible data rate of 2.5Gbit/s. In addition to the PIN photodiode attached to a transimpedance amplifier it also includes a decision circuit and a 50Ω output driver. The measured bandwidth of the receiver of 1.90GHz is sufficient for 2.5Gbit/s. At an optical wavelength of 660nm, a sensitivity of -17.0dBm was measured. At a supply voltage of 5V, the power consumption of the complete receiver is 171mW, from which the output driver requires 128mW. The overall chip size is 1154μm times 727μm.
We present an optical fiber receiver which includes a monolithically integrated PIN photodiode, a transimpedance amplifier, a decision circuit and a PECL compatible output driver. This low-cost and low-power receiver was fabricated in 0.6μm BiCMOS technology. Only one minor process modification was necessary to implement the PIN photodiodewith a diameter of 150μm. A minimum number of external components is needed for interfacing with standard PECL gates. At a maximum possible data rate of 625Mbit/s, a sensitivity of -22.7dBm was measured at an optical wavelength of 660nm. At a single-supply voltage of 5V, the power consumption of the complete receiver is less than 74mW. The overall chip size is 1763μm times 648μm.
We present a system for direct parallel optical data communication between integrated circuits on neighboured printed circuit boards based on a monolithic integrated CMOS smart pixel array, fibre arrays, and VCSELs. The advantage of our system versus backplane systems is the direct data transfer through the space avoiding planar and area consuming interconnections. The detector chip allows a data rate of 625 Mbit/s per link and is cycled by an optical clock. A simulation of the chip layout showed 260 % more performance versus electrical off-chip interconnects. In principle an 8'8 data transfer is feasible allowing a data rate of 40 Gbit/s. The detector combines an optical receiver array with a digital processor array which executes image processing algorithms. The optical receiver is formed by a PIN photodiode with a diameter of 40 µm, a transimpedance amplifier (TIA) and a decision-making postamplifier. The measured responsivity of the photodiode without antireflection coating is R=0.382 A/W at an optical wavelength of 670 nm. The TIA consists of a CMOS inverter and a PMOS transistor forming the feedback resistor. Together with the postamplifier, formed by a chain of five CMOS inverters and attaining digital CMOS levels, a data rate of 625 Mbit/s is achieved.
Generally, a high-speed optical sensor consists of a photodiode and a transimpedance amplifier. If a large photosensitive area is demanded, the resulting large junction capacitance of the photodiode limits both the bandwidth and the noise behavior of the transimpedance amplifier. Therefore we suggest an innovative approach, which divides the photodiode into four electrically isolated sections. Each of the four-quarter photodiodes is connected to a transimpedance amplifier and their output voltages are combined with a summation amplifier. The capacitance of each of the four-quarter photodiodes is only one fourth of the capacitance of the undivided photodiode, therefore the bandwidth of the innovative optical sensor is 223MHz, which is three times as high as the bandwidth of a transimpedance amplifier with an undivided photodiode. The photo-sensitivity is more than doubled to 75mV/μW.