With extreme UV not ready for HVM for the 20nm and 14nm nodes, double patterning options that extend the use of 193nm immersion lithography beyond the optical resolution limits, such as LELE (Litho-Etch-Litho-Etch) and SADP (Self Aligned Double Patterning), are being used for critical layers for these nodes. LELE requires very stringent overlay capability of the optical exposure tool. The spacer scheme of SADP starts with a conformal film of material around the mandrels and etched along the mandrel sidewalls to form patterns with doubled frequency. SADP, while having the advantage of being a self-aligned process, adds a number of process steps and strict control of the mandrel profile is required. In this paper, we will demonstrate a novel technique - ASDP (Anti-Spacer Double Patterning), which uses only spin-on materials to achieve self-aligned double patterning. After initial resist patterning, an Anti-Spacer Generator (ASG) material is coated on the resist pattern to create the developable spacer region. Another layer of material is then coated and processed to generate the second pattern in between the first resist pattern. We were able to define 37.5nm half pitch pattern features using this technique as well as sub-resolution features for an asymmetric pattern. In this paper we will review the capability of the process in terms of CD control and LWR (line width roughness) and discuss the limitations of the process.
Chemical flare has been shown to be a process limiter for patterns that are surrounded by areas of unexposed resist for
certain chemically amplified resists. Using a pattern known to be susceptible to chemical flare effect a method was
developed and tested on several materials. Details of the testing patterns, consisting of placements of small and large
pattern density areas set to provide multiple degrees of resist loading; and a second level of loading variation achieved by
selective exposure locations of those patterns across the wafer are given. Descriptions of the determination of slopes from
linear trend-lines of the critical dimensions responses can be used to provide a gauge for internal evaluations as well as
feedback to the vendors for chemical flare sensitivity.
As the industry drives to lower k1 imaging we commonly accept the use of higher NA imaging and advanced
illumination conditions. The advent of this technology shift has given rise to very exotic pupil spread functions that
have some areas of high thermal energy density creating new modeling and control challenges. Modern scanners are
equipped with advanced lens manipulators that introduce controlled adjustments of the lens elements to counteract the
lens aberrations existing in the system. However, there are some specific non-correctable aberration modes that are
detrimental to important structures. In this paper, we introduce a methodology for minimizing the impact of aberrations
for specific designs at hand. We employ computational lithography to analyze the design being imaged, and then devise
a lens manipulator control scheme aimed at optimizing the aberration level for the specific design. The optimization
scheme does not minimize the overall aberration, but directs the aberration control to optimize the imaging performance,
such as CD control or process window, for the target design. Through computational lithography, we can identify the
aberration modes that are most detrimental to the design, and also correlations between imaging responses of
independent aberration modes. Then an optimization algorithm is applied to determine how to use the lens manipulators
to drive the aberrations modes to levels that are best for the specified imaging performance metric achievable with the
tool. We show an example where this method is applied to an aggressive memory device imaged with an advanced ArF
scanner. We demonstrate with both simulation and experimental data that this application specific tool optimization
successfully compensated for the thermal induced aberrations dynamically, improving the imaging performance
consistently through the lot.
Scanner matching based on wafer data has proven to be successful in the past years, but its adoption into production has
been hampered by the significant time and cost overhead involved in obtaining large amounts of statistically precise
wafer CD data. In this work, we explore the possibility of optical model based scanner matching that maximizes the use
of scanner metrology and design data and minimizes the reliance on wafer CD metrology.
A case study was conducted to match an ASML ArF immersion scanner to an ArF dry scanner for a 6Xnm technology
node. We used the traditional, resist model based matching method calibrated with extensive wafer CD measurements
and derived a baseline scanner manipulator adjustment recipe. We then compared this baseline scanner-matching recipe
to two other recipes that were obtained from the new, optical model based matching method. In the following sections,
we describe the implementation of both methods, provide their predicted and actual improvements after matching, and
compare the ratio of performance to the workload of the methods. The paper concludes with a set of recommendations
on the relative merits of each method for a variety of use cases.
Bilayer, Si-containing resists are a technique of interest and a strong candidate to replace chemical vapor deposition
(CVD) hardmask processes for small critical dimensions (CDs). Previously, we proposed a very thin film approach using
bilayer resists for future lithography, defined the requirements for the resists, and demonstrated 55nm transferred
patterns with high aspect ratios using 2-beam interferometer exposure. In this paper, we have demonstrated smaller-than-
60nm transferred patterns with a high numerical aperture (NA) scanner, as well as 45nm and 40nm transferred patterns
with a 2-beam system using a 20% Si-containing thin bilayer resist. Immersion scanner exposure and a 35nm CD with 2-
beam system were also studied.
Resist aspect ratio has always been an issue for lithographic processes. Smaller CD forces the use of thinner resist films, but dry etch needs a certain amount of thickness in the resist. Various techniques have been proposed and researched to overcome these single-layer resist limitations. Bilayer Si-containing resists are a technique of interest and a strong candidate to replace CVD processes. In this paper, we have characterized bilayer resists and their dry-develop processes, and sought possible uses for advanced lithography, especially by using a thin film (70nm-90nm). Bilayer resist dry-develop consists of a film shrink as in an exposure reaction with an early-stage resist surface oxidation. We discuss material requirements for this purpose and provide some after-dry-develop images with small CD.