Proceedings Article | 28 May 2004
Proc. SPIE. 5377, Optical Microlithography XVII
KEYWORDS: Lithography, Diffraction, Reticles, Polarization, Opacity, Chromium, Photomasks, SRAF, Semiconducting wafers, Resolution enhancement technologies
Much has been made of the term 'subwavelength' in the lithography community in recent years, referring to the smaller feature sizes that the International Technology Roadmap for Semiconductors (ITRS) demands. This term, however, has additional meaning when the features on the reticle, rather than on the wafer, are smaller than the wavelength. In this case, all assumptions that are made concerning the (lack of) diffraction in the immediate vicinity of the reticle in conventional simulation algorithms - including that in model-based optical proximity correction (MBOPC) software - become invalid. As has been repeatedly shown, one must resort to a vector representation of the illumination and solve Maxwell's equations in order to properly characterize the electric field beyond the reticle. For the 90 and 65 nm nodes, resolution enhancement features such as subresolution assist features (SRAFs) and alternating phase-shift masks (Alt-PSM) require such analysis for accurate modeling. Furthermore, if the industry continues a push to use 193 nm lithography for the 45 nm node, and if the current 4X reduction infrastructure also remains, then all critical features will require this full vectorial solution to maintain acceptable accuracy in simulations. Furthermore, the simultaneous push to increasingly higher values of the numerical aperture - beyond 0.85 - requires that the polarization of the light in the exit pupil of the projection lens be considered. Although the ability to simulate this phenomenon has existed in standard simulation software, there remain issues that are not well understood by the community. These questions go beyond the difficulty of such simulations: it is never a question that someone will write software to model these scenarios. The real problem lies in runtime: many of these problems require an increase in runtime of an order of magnitude, or more, in a production model-based OPC environment, which translates into increased cycle time and cost per chip. This is in addition to the expected loss in process latitude caused by unintentional polarization phenomena. One may be tempted to assume that these problems will go away by relaxing the reduction ratio beyond 4X to, say, 8X; that is, by increasing the critical dimension (CD) on the mask. While this is indeed likely, more practical problems inevitably creep in, the most serious of these being throughput loss. The economic issues, and not technical ones, has kept the reduction ratio fixed in the face of the lithographic difficulties we as an industry face going forward. Nevertheless, as we hurriedly investigate technologies that seemed exploratory not long ago, the technical aspects of increasing the reduction ratio beyond 4X are worth another look. Clearly, EMF effects will decrease, but not vanish; how much of an impact this has on our ability to simulate quickly and obtain reasonable process windows in the EMF regime for 4X is a goal of this paper.
