This paper introduces a defect tolerant 64-bit Sklansky prefix adder, designed with the goal of increasing its
reliability and extending its lifetime in the presence of hard faults. We consider defect tolerance for early
transistor wear-out by exploring the design of fine-grained reconfigurable logic. The approach involves enabling
spare processing elements to replace defective elements. Power gating techniques are used to disable faulty logic
blocks and enable spare logic. Minimum sized transistors are used for spare processing elements to reduce area
overhead, and simplify reconfiguration interconnect.
The performance of the design is compared to a baseline, non-repairing design using the cost metrics of: area
overhead, power consumption, and performance in the fault free and faulty case.
Random low-density parity-check (LDPC) codes have been shown to have better performance compared to structured codes because of their better minimum distance and girth. However, random codes result in decoders with large VLSI area and complex routing. The routing complexity is the main limitation for implementing practical fully parallel LDPC decoders. We use reordering sparse-matrix algorithms to reduce the average wire-length and congestion in fully parallel VLSI implementations. Rows and columns of the code matrix are rearranged such that each row/column connection is as close as possible. The restructuring achieves a 15% reduction in average wire-length and 30% in reducing the number of wires across an area. The shape of restructured code is predictable making it possible to develop better routing algorithms for such codes. The shape of the code also simplifies routing in that consecutive rows have almost the same range. Restructuring of the matrix does not change the code matrix and hence does not affect its performance.
The design of common source (CS) Low Noise Amplifiers (LNA) for wireless receivers is presented. The design trade-offs between main criteria are discussed. An extra gate-to-source capacitor is added to the input transistor to reduce the transistor dimension while still satisfying the noise matching. The small MOSFET also improves the LNA linearity with comparatively small drain-source current. The extra gate-to-source capacitor is introduced by the bonding-pad parasitic capacitor; hence a negative effect parasitic capacitance is turned into a useful capacitor. The simulated Noise Figure (NF) of two single-ended LNAs using 0.18 μm CMOS process achieve 0.62 dB and 0.92 dB at 2.4 GHz and 5.25 GHz respectively while matching a 50 ohm impedance.
This paper presents the design of a 1 GHz continuous-time second order Lowpass Sigma Delta Modulator (LPSDM). The design is intended to meet the future requirements of wideband wireless receivers. The continuous-time Noise Transfer Function (NTF) for the modulator is realized using two Gm-C integrators with negative transconductance feedback and three linearized Gm elements. A three-stage delayed comparator is employed for designing the one bit quantizer, therefore a delayed NTF had to be synthesized. The presented target design is 0.18μm CMOS process. The designed chip uses both 3.3V and 1.8V MOSFETs and consumes 80mW including the clock driver and the output buffer. The performance of the modulator based on post layout simulation is 11 bits for a 5 MHz bandwidth and 8.6 bits for an 11MHz bandwidth.
In wideband surveillance and digital radio systems, there is a need to sweep the centre fequency of the data converter to detect a broadcast i nthe band of interest. Hence there is a need to design data converters with variable centre frequencies. Sigma-Delta modulators with programmable center frequency are chosen for this purpose. In this paper new resonators for a variable centre frequency bandpass Sigma-Delta modulator are presented. The new resonators have a centre frequency that extends from very low frequency up to half the sampling frequency. Simulation results of a fourth order discrete-time bandpass modulator employing the new resonator are presented using MATLAB and SPICE.
Proc. SPIE. 4593, Design, Characterization, and Packaging for MEMS and Microelectronics II
KEYWORDS: Digital signal processing, 3D applications, Computer programming, 3D modeling, Very large scale integration, Time division multiplexing, Chemical elements, Algorithm development, Computer graphics, Product engineering
Parallel multipliers are of increasing importance for VLSI design, largely driven by the significant increase in demand for computer graphics and digital signal processing. The fastest (and, when pipelined, most area-efficient) multiplier class is partial product reduction tree (PPRT) based multipliers. The previous best known heuristic for PPRT design (published by Stelling et al.) is capable of producing the fastest possible circuits but suffers an infeasible computational burden. This paper introduces some results which significantly reduce the search space of this heuristic. Consequently, the speed of netlist generation is increased, and the circuits generated retain optimal performance. In addition, larger optimal multipliers may be synthesised due to the easing of the computational burden.