Since its introduction more than a decade ago, inverse lithography technology (ILT) has been seen as a promising solution to many of the challenges of advanced-node lithography. Numerous studies have demonstrated that curvilinear ILT mask shapes produce the best process window. However, the runtimes associated with this computational technique have limited its practical application. In 2019, D2S introduced an entirely new, stitchless approach for ILT . This system includes a unique GPU-accelerated approach that emulates a single, giant GPU/CPU pair that can compute an entire full-chip ILT solution at once. This novel approach, systematically designed for ILT and GPU acceleration, makes full-chip ILT a practical reality in production for the first time. The masks used to validate wafer results for this system were written by a multi-beam mask writer. The question remained of whether it was possible to use this new approach to ILT in a way that could be written by a variable-shaped beam (VSB) mask writer. This paper introduces a new method, in which a process called mask-wafer cooptimization (MWCO) is performed during ILT optimization. This new approach enables curvilinear ILT for 193i masks to be written on VSB mask writers within reasonable write times. It shortens the total turnaround time so that VSB mask writers can produce full-chip, curvilinear ILT masks within a practical, 12-hour time frame, while also producing the largest process windows. It should be noted that this enables curvilinear or any-angle targets for the wafer design to be processed by curvilinear ILT and then written by VSB mask writers for 193i processes. While MWCO as a concept can be used for multi-beam mask writers as well, this paper is focused on MWCO for VSB mask writers.
Deep learning has an increasing impact on our personal and professional lives. Deep learning has the potential to transform mask, semiconductor and electronics manufacturing. This paper reviews key results from the Center for Deep Learning in Electronics Manufacturing’s (CDLe’s) first year of operation. We consider results from adapting five common types of deep learning recipes to solve key challenges in the manufacture of photomasks, printed circuit boards (PCBs), and flat panel displays (FPDs). These deep learning applications include 1) grouping similar items to automatically categorize mask rule errors; 2) using U-Net architecture to construct fast mask designs; 3) using vision-based object classification to find and classify pick-and-place (PnP) errors on PCB assembly lines; 4) using anomaly detection to improve the quality of FPDs; and 5) using digital twins to create SEM images and optimize Inverse Lithography Technology (ILT). While we compare the relative benefits of these techniques, all show the importance of data to improve the success of deep learning networks and of electronics manufacturing. These applications rely on varying neural network architectures such as autoencoders, segmentation networks, deep convolutional networks, anomaly detection, and generative adversarial networks (GANs).
Inverse Lithography Technology (ILT) is becoming the choice for Optical Proximity Correction (OPC) of advanced technology nodes in IC design and production. Multi-beam mask writers promise significant mask writing time reduction for complex ILT style masks. Before multi-beam mask writers become the main stream working tools in mask production, VSB writers will continue to be the tool of choice to write both curvilinear ILT and Manhattanized ILT masks. To enable VSB mask writers for complex ILT style masks, model-based mask process correction (MB-MPC) is required to do the following: 1). Make reasonable corrections for complex edges for those features that exhibit relatively large deviations from both curvilinear ILT and Manhattanized ILT designs. 2). Control and manage both Edge Placement Errors (EPE) and shot count. 3. Assist in easing the migration to future multi-beam mask writer and serve as an effective backup solution during the transition. In this paper, a solution meeting all those requirements, MB-MPC with GPU acceleration, will be presented. One model calibration per process allows accurate correction regardless of the target mask writer.
For IC design starts below the 20nm technology node, the assist features on photomasks shrink well below 60nm and the printed patterns of those features on masks written by VSB eBeam writers start to show a large deviation from the mask designs. Traditional geometry-based fracturing starts to show large errors for those small features. As a result, other mask data preparation (MDP) methods have become available and adopted, such as rule-based Mask Process Correction (MPC), model-based MPC and eventually model-based MDP.
The new MDP methods may place shot edges slightly differently from target to compensate for mask process effects, so that the final patterns on a mask are much closer to the design (which can be viewed as the ideal mask), especially for those assist features. Such an alteration generally produces better masks that are closer to the intended mask design. Traditional XOR-based MDP verification cannot detect problems caused by eBeam effects. Much like model-based OPC verification which became a necessity for OPC a decade ago, we see the same trend in MDP today.
Simulation-based MDP verification solution requires a GPU-accelerated computational geometry engine with simulation capabilities. To have a meaningful simulation-based mask check, a good mask process model is needed. The TrueModel® system is a field tested physical mask model developed by D2S. The GPU-accelerated D2S Computational Design Platform (CDP) is used to run simulation-based mask check, as well as model-based MDP. In addition to simulation-based checks such as mask EPE or dose margin, geometry-based rules are also available to detect quality issues such as slivers or CD splits. Dose margin related hotspots can also be detected by setting a correct detection threshold.
In this paper, we will demonstrate GPU-acceleration for geometry processing, and give examples of mask check results and performance data. GPU-acceleration is necessary to make simulation-based mask MDP verification acceptable.