Mr. Michael L. Rieger Profile

Michael L. Rieger

Consultant at Rieger Strategic Innovation, LLC

SPIE Involvement:

Conference Program Committee | Author

Publications (36)

SPIE Journal Paper | 26 November 2019 Open Access

Retrospective on VLSI value scaling and lithography

Michael Rieger

JM3, Vol. 18, Issue 04, 040902, (November 2019) https://doi.org/10.1117/12.10.1117/1.JMM.18.4.040902

KEYWORDS: Transistors, Lithography, Very large scale integration, Clocks, Switching, Capacitance, Photomasks, Silicon, Logic, Resolution enhancement technologies

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SPIE Journal Paper | 1 March 2012

Communication theory in optical lithography

Michael Rieger

JM3, Vol. 11, Issue 1, 013003, (March 2012) https://doi.org/10.1117/12.10.1117/1.JMM.11.1.013003

KEYWORDS: Lithography, Photomasks, Optical lithography, Communication theory, Image processing, Channel projecting optics, Materials processing, Double patterning technology, Extreme ultraviolet, Diffraction

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Proceedings Article | 4 April 2007 Paper

Comparing traditional OPC to field-based OPC for 45-nm node production

Rick Farnbach, Josh Tuttle, Matt St. John, Randy Brown, Dave Gerold, Kevin Lucas, Robert Lugg, James Shiely, Mike Rieger

Proceedings Volume 6520, 65204F (2007) https://doi.org/10.1117/12.721593

KEYWORDS: Optical proximity correction, Computer simulations, Image segmentation, Semiconducting wafers, Control systems, Photomasks, Mathematical modeling, Manufacturing, Convolution, Image analysis

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Proceedings Article | 27 March 2007 Paper

Patterning control budgets for the 32-nm generation incorporating lithography, design, and RET variations

Kevin Lucas, Chris Cork, Jonathan Cobb, Brian Ward, Martin Drapeau, Charlie Zhang, John Allgair, Mike Kling, Mike Rieger

Proceedings Volume 6520, 65200N (2007) https://doi.org/10.1117/12.715166

KEYWORDS: Optical lithography, Optical proximity correction, Error analysis, Resolution enhancement technologies, SRAF, Lithography, OLE for process control, Photomasks, Manufacturing, Metrology

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An important outcome of the 90nm and 65nm device generations was the realization that new methods for predicting and controlling patterning were required to ensure successful transfer for all design rule compliant features through the required process window. This realization led to a strong increase in the use of CD-based and process window aware post-optical proximity correction (OPC) verification in production mask tapeouts. Accurate post-OPC verification is a necessity but many patterning issues could have been detected and removed earlier in the product development lifecycle. Of course, the 45nm and 32nm device generations are only expected to further strain the ability of device manufacturers to predict process control requirements, robust patterning design rules and first-time right reticle enhancement technology (RET) recipes. Therefore, improvements to the traditional process, OPC and design rule prediction/evaluation steps are needed. In this paper we propose a patterning and CD control prediction methodology which incorporates not only the traditional dose, defocus and mask variation parameters but also implements RET parameter variations such as layout edge discretization, model inaccuracy, metrology error and assist feature placement. This methodology allows a more accurate prediction of process control requirements, worst case CD control layout geometries and RET subsystem accuracy/control requirements. Lithography engineers have long operated with specific (if not always fully understood) dose and focus control success requirements. To efficiently determine real worst design situations, we utilize a new methodology for quickly verifying the RET-ability of a lithography process + design rule set + OPC correction recipe based on coupling iterative layout generation with OPC testing. Our aim in this paper is to provide additional engineering rigor to the traditional experience-based OPC success requirements by looking at the total Litho + RET + metrology patterning problem and analyzing the individual component control needs.

Proceedings Article | 5 May 2005 Paper

Process centering OPC using design intent to improve yield

Michel Cote, Alexander Miloslavsky, Robert Lugg, Michael Rieger, Philippe Hurat

Proceedings Volume 5756, (2005) https://doi.org/10.1117/12.600180

KEYWORDS: Optical proximity correction, Tolerancing, Silicon, Process modeling, Metals, Image processing, Manufacturing, Yield improvement, Critical dimension metrology, Printing

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Proceedings Article | 5 May 2005 Paper

Mask cost reduction and yield optimization using design intent

Michel Cote, Alexander Miloslavsky, Philippe Hurat, Michael Rieger, Denis Goinard

Proceedings Volume 5756, (2005) https://doi.org/10.1117/12.600086

KEYWORDS: Tolerancing, Photomasks, Optical proximity correction, Metals, Resolution enhancement technologies, Manufacturing, Printing, Yield improvement, Computed tomography, Process modeling

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Proceedings Article | 6 December 2004 Paper

Placing assist features in layout using a process model

Lawrence Melvin, James Shiely, Michael Rieger

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.569179

KEYWORDS: SRAF, Atrial fibrillation, Process modeling, Model-based design, Destructive interference, Lithography, Optical proximity correction, Constructive interference, Critical dimension metrology, Semiconducting wafers

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Proceedings Article | 6 December 2004 Paper

Maintaining lithographic quality during OPC for low-k1 and MEEF processes constrained by mask dimensional rules

Christopher Cork, Lawrence Melvin, Michael Miller, Robert Lugg, Michael Rieger

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.568550

KEYWORDS: Optical proximity correction, Photomasks, Lithography, Image segmentation, Silicon, Model-based design, Mask making, Semiconducting wafers, Resolution enhancement technologies, Transistors

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Proceedings Article | 20 August 2004 Paper

Model-based interpretation filtering for complex two-dimensional layout features

Lawrence Melvin, James Shiely, Christopher Cork, Michael Rieger

Proceedings Volume 5446, (2004) https://doi.org/10.1117/12.557742

KEYWORDS: Model-based design, Optical proximity correction, Process modeling, Detection and tracking algorithms, Data modeling, Optical lithography, Image processing, Photoresist materials, Performance modeling, Data processing

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Proceedings Article | 28 May 2004 Paper

Classical control theory applied to OPC correction segment convergence

Benjamin Painter, Lawrence Melvin, Michael Rieger

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.537586

KEYWORDS: Control systems, Optical proximity correction, Data modeling, Process control, Data corrections, Image processing, Data centers, Process modeling, Model-based design, Systems modeling

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Proceedings Article | 28 May 2004 Paper

Advanced model formulations for optical and process proximity correction

Daniel Beale, James Shiely, Lawrence Melvin, Michael Rieger

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.544258

KEYWORDS: Etching, Data modeling, Optical proximity correction, Calibration, Image processing, Scanning electron microscopy, Photoresist processing, Model-based design, Process modeling, Point spread functions

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As post-litho process effects account for a larger and larger portion of CD error budgets, process simulation terms must be given more weight in the models used for proximity correction. It is well known that for sub-90 nm processes resist and etch effects can no longer be treated as a small perturbation on a purely optical (aerial image) OPC model. The aerial image portion of the model must be combined in a more appropriate way with empirical terms describing resist and etch effects. The OPC engineer must choose a model form which links an optical component with a resist/etch component in a manner that balances efficiency, robustness and fidelity to the aerial image, among other factors. No single way of connecting litho and etch models is ideal in all cases; the best form of linkage depends on the particular litho and etch process to be simulated. In this paper, we provide practical guidelines for linking litho and etch components of a model, using a representative 70 nm process with a large etch bias as an example. This 70 nm case study, which is representative of many sub-90 nm processes that rely on etch to shrink critical features, presents special challenges for OPC modeling. For the process under study, lines were are printed in resist at 120 nm, and the litho model was verified via resist SEM measurements taken at the resist edge. Note that a thresholded aerial image is not well-characterized a distance 25 nm from the resist edge. This is roughly the distance the edge moves back due to the etch step. Although in some cases etch bias can be calculated from aerial image contrast, in general etch bias cannot be predicted from the aerial image because litho and etch are governed by different underlying physics. The model forms available for linking litho and etch range from the efficient “lumped” form, which combines litho and etch simulation in a single model, to a highly accurate two-stage form which separates the two components. In this paper we evaluate the following model forms for applicability to the 70 nm process under study: 1) Aerial image/load kernel combined (“lumped”) model form 2) Aerial image/rule offset “hybrid” model form 3) Separate litho and etch models (2-stage correction)

Proceedings Article | 3 May 2004 Paper

Mathematically describing the target contour in silicon such that model-based OPC can best realize design intent

Christopher Cork, Pratheep Balasingam, Sonya Sandvik, Bill Kielhorn, Michael Rieger

Proceedings Volume 5379, (2004) https://doi.org/10.1117/12.538047

KEYWORDS: Optical proximity correction, Critical dimension metrology, Photomasks, Silicon, Mathematical modeling, Transistors, Semiconducting wafers, Diffusion, Model-based design, Image processing

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Proceedings Article | 17 December 2003 Paper

Model-based methodology for reducing OPC output pattern complexity

Lawrence Melvin, Michael Rieger

Proceedings Volume 5256, (2003) https://doi.org/10.1117/12.518331

KEYWORDS: Optical proximity correction, Model-based design, Image segmentation, Data modeling, Reticles, Process modeling, Bridges, Inspection, Data processing, Manufacturing

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One of the best methods to increase correction accuracy in model based OPC is to decrease the correction segment length. As design rules shrink, this methodology is becoming more prevalent in model based OPC corrections. Unfortunately, it increases general mask feature complexity, which leads to reticles that are difficult to manufacture and inspect. With current OPC segmentation methodologies, the smallest correction segment length is generally applied uniformly across an entire correction set. A more targeted segmentation approach using the process model to determine sampling rates and locations could be used to confine complex correction features only to regions where they are absolutely necessary. For example, the choice between a hammerhead or dog-ear serif can be made using process model data so that dog-ear serifs are only used when flat aerial images are generated by the layout. This would lead to a more frugal correction that maintains correction accuracy while reducing mask construction complexity. OPC complexity is a key factor driving mask costs higher as design rules are pushed smaller. Methods for effectively reducing OPC complexity, without compromising OPC effectiveness, are being leveraged to help reduce the rate of NRE cost growth. In previous papers we have discussed methods for identifying features in which OPC accuracy can be sacrificed safely to reduce mask complexity. In addition, we have outlined methods for handling process variation effects for simple OPC shapes in complex regions. In this paper we will discuss another method for reducing OPC complexity while optimally preserving OPC accuracy on every feature. The method leverages pre-correction process simulation to predict the most “cost effective” shape for a feature. With simulated pattern characteristics and with consideration of potential mask rule violations, the method establishes an optimum correction shape “template.” For example, the choice between various line end-treatments can be determined up front, thus focusing the OPC computation on the most effective and least complex shape, and removing the need to perform post-OPC mask constraint shape adjustments. The implementation of this methodology leads to a more frugal correction that maintains correction accuracy while reducing mask construction complexity.

Proceedings Article | 28 August 2003 Paper

Anticipating and controlling mask costs within EDA physical design

Michael Rieger, Jeffrey Mayhew, Lawrence Melvin, Robert Lugg, Daniel Beale

Proceedings Volume 5130, (2003) https://doi.org/10.1117/12.504270

KEYWORDS: Photomasks, Optical proximity correction, Tolerancing, Silicon, Semiconducting wafers, Lithography, Vestigial sideband modulation, Inspection, Model-based design, Electronic design automation

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For low k1 lithography, more aggressive OPC is being applied to critical layers, and the number of mask layers with OPC treatments is growing rapidly. The 130 nm, process node required, on average, 8 layers containing rules- or model-based OPC. The 90 nm node will have 16 OPC layers, of which 14 layers contain aggressive model-based OPC. This escalation of mask pattern complexity, coupled with the predominant use of vector-scan e-beam (VSB) mask writers contributes to the rising costs of advanced mask sets. Writing times for OPC layouts are several times longer than for traditional layouts, making mask exposure the single largest cost component for OPC masks. Lower mask yields, another key factor in higher mask costs, is also aggravated by OPC. Historical mask set costs are plotted below. The initial cost of a 90 nm-node mask set will exceed one million dollars. The relative impact of mask cost on chip depends on how many total wafers are printed with each mask set. For many foundry chips, where unit production is often well below 1000 wafers, mask costs are larger than wafer processing costs. Further increases in NRE may begin to discourage these suppliers' adoption to 90 nm and smaller nodes. In this paper we will outline several alternatives for reducing mask costs by strategically leveraging dimensional margins. Dimensional specifications for a particular masking layer usually are applied uniformly to all features on that layer. As a practical matter, accuracy requirements on different features in the design may vary widely. Take a polysilicon layer, for example: global tolerance specifications for that layer are driven by the transistor-gate requirements; but these parameters over-specify interconnect feature requirements. By identifying features where dimensional accuracy requirements can be reduced, additional margin can be leveraged to reduce OPC complexity. Mask writing time on VSB tools will drop in nearly direct proportion to reduce shot count. By inspecting masks with reference to feature-dependent margins, instead of uniform specifications, mask yield can be effectively increased further reducing delivered mask expense.

Proceedings Article | 26 June 2003 Paper

A methodology to calculate line-end correction feature performance as a function of reticle cost

Lawrence Melvin, James Shiely, Michael Rieger, Benjamin Painter

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485533

KEYWORDS: Reticles, Lithography, Head, Optical proximity correction, Photomasks, Ear, Mask making, Data corrections, Manufacturing, Performance modeling

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Proceedings Article | 26 June 2003 Paper

Multiple-stage optical proximity correction

Daniel Beale, James Shiely, Michael Rieger

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.488804

KEYWORDS: Etching, Photomasks, Model-based design, Data modeling, Semiconducting wafers, Optical calibration, Optical proximity correction, Data corrections, Lithography, Projection systems

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Proceedings Article | 27 December 2002 Paper

Programmable RET mask layout verification

Daniel Beale, Jeffrey Mayhew, Michael Rieger, Zongwu Tang

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.471299

KEYWORDS: Photomasks, Resolution enhancement technologies, Optical proximity correction, Tolerancing, Lithography, Silicon, Semiconducting wafers, Model-based design, Manufacturing, Bridges

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Proceedings Article | 27 December 2002 Paper

Effective distributed architecture for OPC and RET applications

Robert Lugg, Mathias Boman, James Burdorf, Michael Rieger

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.471300

KEYWORDS: Data communications, Optical proximity correction, Resolution enhancement technologies, Data modeling, Sun, Parallel processing, Distributed computing, Telecommunications, Computer architecture, Parallel computing

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Proceedings Article | 1 August 2002 Paper

Enriching design intent for optimal OPC and RET

Michael Rieger, Valery Gravoulet, Jeffrey Mayhew, Daniel Beale, Robert Lugg

Proceedings Volume 4754, (2002) https://doi.org/10.1117/12.476939

KEYWORDS: Optical proximity correction, Photomasks, Silicon, Tolerancing, Resolution enhancement technologies, Transistors, Model-based design, Lithography, Manufacturing, Integrated circuit design

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Proceedings Article | 30 July 2002 Paper

Adaptive OPC with a conformal target layout

Robert Lugg, Daniel Beale, Jason Huang, Michael Rieger

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474488

KEYWORDS: Photomasks, Optical proximity correction, Tolerancing, Critical dimension metrology, Silicon, Image processing, Semiconducting wafers, Model-based design, Lithography, Image enhancement

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In its purest form optical proximity correction (OPC) creates a mask layout to faithfully reproduce the design intent, or target, on silicon. Practical, production-worthy OPC deviates from this ideal in several respects. First, each set of anticipated process conditions -- defocus, dose -- would require a unique ideal correction. An optimized OPC shape must be derived to minimize harm over the expected ranges of process conditions. Second, the original design layout does not always convey accurate or complete information about the design intent. For example, square corners cannot be printed; how much corner rounding is acceptable? Some legacy design practices, such as line-end extension rules, anticipate (in part) proximity-effects where the intended line end is shorter than drawn. Without additional information, the OPC tool is constrained to aim for the one silicon layout matching the drawn layout as closely as possible. On the other hand, if the OPC tool is given limited liberty to deviate from drawn shapes and positions where they have little or no impact on circuit behavior the correction can be better optimized for several, sometimes competing, constraints - such as: minimizing output figure complexity, minimizing CD error through process variation, maximizing image contrast, and minimizing mask error enhancement factor. In this paper we will demonstrate OPC strategies for optimizing corrections to minimize the harmful effects of random process variations while simultaneously minimizing mask layout complexity. We introduce the concept of a 'conformal target' layout which enhances the drawn pattern with design-intent tolerance information. This information specifies bounds on minimum line and space dimensions, line position, and edge position. Such feature-specific tolerance information provides additional degrees of freedom for OPC synthesis to optimize trade-offs among process window behavior, contrast, MEEF reduction, output figure complexity, and other fab-specific objectives. Furthermore, the tolerance-based conformal target provides an ideal reference pattern for verifying OPC and other resolution enhancement treatments (RET) on the mask layout.

Proceedings Article | 12 July 2002 Paper

Verifying RET mask layouts

Jeffrey Mayhew, Michael Rieger, Jiangwei Li, Lin Zhang, Zongwu Tang, James Shiely

Proceedings Volume 4692, (2002) https://doi.org/10.1117/12.475670

KEYWORDS: Resolution enhancement technologies, Photomasks, Tolerancing, Optical proximity correction, Semiconducting wafers, Process modeling, Lithography, Model-based design, Metals, Manufacturing

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Proceedings Article | 11 March 2002 Paper

OPC strategies to minimize mask cost and writing time

Michael Rieger, Jeffrey Mayhew, Jiangwei Li, James Shiely

Proceedings Volume 4562, (2002) https://doi.org/10.1117/12.458287

KEYWORDS: Optical proximity correction, Tolerancing, Photomasks, Semiconducting wafers, Databases, Prototyping, Manufacturing, Lithography, Mask making, Model-based design

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Proceedings Article | 22 January 2001 Paper

Dual-mask model-based proximity correction for high-performance 0.10-um CMOS process

Shane Palmer, Mark Mason, John Randall, Tom Aton, Keeho Kim, Alexander Tritchkov, James Burdorf, Michael Rieger, John Stirniman

Proceedings Volume 4186, (2001) https://doi.org/10.1117/12.410679

KEYWORDS: Optical proximity correction, Photomasks, Binary data, Data modeling, Etching, Phase shifts, Optical lithography, Databases, Critical dimension metrology, Semiconducting wafers

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Proceedings Article | 5 July 2000 Paper

Understanding the parameters for strong phase-shift mask lithography

Alexander Tritchkov, John Stirniman, Jeffrey Mayhew, Michael Rieger

Proceedings Volume 4000, (2000) https://doi.org/10.1117/12.388970

KEYWORDS: Photomasks, Semiconducting wafers, Lithography, Optical proximity correction, Critical dimension metrology, Manufacturing, Binary data, Phase shifts, Error analysis, Systems modeling

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Proceedings Article | 26 July 1999 Paper

Alternating PSM optimization using model-based OPC

Alexander Tritchkov, John Stirniman, Michael Rieger

Proceedings Volume 3679, (1999) https://doi.org/10.1117/12.354368

KEYWORDS: Photomasks, Optical proximity correction, Critical dimension metrology, Phase shifts, Binary data, Nanoimprint lithography, Lithography, Semiconducting wafers, Image processing, Optimization (mathematics)

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Proceedings Article | 7 July 1997 Paper

Spatial-filter models to describe IC lithographic behavior

John Stirniman, Michael Rieger

Proceedings Volume 3051, (1997) https://doi.org/10.1117/12.275978

KEYWORDS: Process modeling, Lithography, Convolution, Semiconducting wafers, Systems modeling, Communication theory, Spatial filters

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Proceedings Article | 7 July 1997 Paper

Optical proximity effects correction at 0.25 um incorporating process variations in lithography

Alexander Tritchkov, Michael Rieger, John Stirniman, Anthony Yen, Kurt Ronse, Geert Vandenberghe, Luc Van den Hove

Proceedings Volume 3051, (1997) https://doi.org/10.1117/12.275990

KEYWORDS: Lithography, Optical proximity correction, Optical calibration, Deep ultraviolet, Printing

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Proceedings Article | 27 December 1996 Paper

Mask fabrication rules for proximity-corrected patterns

Michael Rieger, John Stirniman

Proceedings Volume 2884, (1996) https://doi.org/10.1117/12.262815

KEYWORDS: Photomasks, Optical proximity correction, Semiconducting wafers, Inspection, Mask making, Image segmentation, Databases, Tolerancing, Convolution, Manufacturing

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Proceedings Article | 7 June 1996 Paper

Customizing proximity correction for process-specific objectives

Michael Rieger, John Stirniman

Proceedings Volume 2726, (1996) https://doi.org/10.1117/12.240930

KEYWORDS: Photomasks, Process modeling, Semiconducting wafers, Data centers, Nano opto mechanical systems, Lithography, Photoresist processing, Integrated circuits, Tolerancing, Custom fabrication

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Proceedings Article | 26 May 1995 Paper

Quantifying proximity and related effects in advanced wafer processes

John Stirniman, Michael Rieger, Robert Gleason

Proceedings Volume 2440, (1995) https://doi.org/10.1117/12.209257

KEYWORDS: Semiconducting wafers, Data modeling, Critical dimension metrology, Photomasks, Wafer-level optics, Cadmium, Data processing, Lithography, Analytical research, Etching

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Proceedings Article | 7 December 1994 Paper

Optimizing proximity correction for wafer fabrication processes

John Stirniman, Michael Rieger

Proceedings Volume 2322, (1994) https://doi.org/10.1117/12.195819

KEYWORDS: Semiconducting wafers, Photomask technology, Silicon, Distance measurement, Data modeling, Structural design, Metrology, Projection systems, Critical dimension metrology, Photomasks

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Proceedings Article | 17 May 1994 Paper

Using behavior modeling for proximity correction

Michael Rieger, John Stirniman

Proceedings Volume 2197, (1994) https://doi.org/10.1117/12.175431

KEYWORDS: Semiconducting wafers, Photomasks, Data modeling, Statistical modeling, Lithography, Process modeling, Convolution, Modeling, Integrated circuits, Etching

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Proceedings Article | 17 May 1994 Paper

Fast proximity correction with zone sampling

John Stirniman, Michael Rieger

Proceedings Volume 2197, (1994) https://doi.org/10.1117/12.175423

KEYWORDS: Semiconducting wafers, Photomasks, Lithography, Mathematical modeling, Data modeling, Phase shifts, Etching, Image processing, Modeling, Nonlinear filtering

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Proceedings Article | 1 June 1992 Paper

Lithographic alternatives to PSM repair

Michael Rieger, Peter Buck, Mark Shaw

Proceedings Volume 1674, (1992) https://doi.org/10.1117/12.130356

KEYWORDS: Photomasks, Semiconducting wafers, Phase shifts, Lithography, Optical lithography, Critical dimension metrology, Printing, Photomicroscopy, Wafer-level optics, Submicron lithography

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Proceedings Article | 1 January 1992 Paper

Specifying phase-shift mask image quality parameters

Peter Buck, Michael Rieger

Proceedings Volume 1604, (1992) https://doi.org/10.1117/12.56954

KEYWORDS: Etching, Photomasks, Phase shifts, Semiconducting wafers, Quartz, Coating, Image quality, Thin film coatings, Control systems, Lithography

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Proceedings Article | 1 July 1991 Paper

Phase-shift mask applications

Peter Buck, Michael Rieger

Proceedings Volume 1463, (1991) https://doi.org/10.1117/12.44806

KEYWORDS: Photomasks, Phase shifts, Manufacturing, Coating, Lithography, Semiconducting wafers, Printing, Phase shifting, Etching, Optical alignment

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Showing 5 of 36 publications

Proceedings Volume Editor (4)

SPIE Conference Volume | 25 March 2011

Design for Manufacturability through Design-Process Integration V

SPIE Conference Volume | 10 March 2010

Design for Manufacturability through Design-Process Integration IV

SPIE Conference Volume | 16 March 2009

Design for Manufacturability through Design-Process Integration III

SPIE Conference Volume | 9 April 2008

Design for Manufacturability through Design-Process Integration II

Conference Committee Involvement (15)

Design-Process-Technology Co-optimization for Manufacturability XI

1 March 2017 | San Jose, California, United States

Design-Process-Technology Co-optimization for Manufacturability X

24 February 2016 | San Jose, California, United States

Design-Process-Technology Co-optimization for Manufacturability IX

25 February 2015 | San Jose, California, United States

Design-Process-Technology Co-optimization for Manufacturability VIII

26 February 2014 | San Jose, California, United States

Design for Manufacturability through Design-Process Integration VII

27 February 2013 | San Jose, California, United States

Design for Manufacturability through Design-Process Integration VI

15 February 2012 | San Jose, California, United States

Design for Manufacturability through Design-Process Integration V

2 March 2011 | San Jose, California, United States

Design for Manufacturability through Design-Process Integration IV

24 February 2010 | San Jose, California, United States

Design for Manufacturability through Design-Process Integration III

26 February 2009 | San Jose, California, United States

Design for Manufacturability through Design-Process Integration II

28 February 2008 | San Jose, California, United States

Design for Manufacturability through Design-Process Integration

1 March 2007 | San Jose, California, United States

Design and Process Integration for Microelectronic Manufacturing IV

23 February 2006 | San Jose, California, United States

Design and Process Integration for Microelectronic Manufacturing IV

3 March 2005 | San Jose, California, United States

Design and Process Integration for Microelectronic Manufacturing III

26 February 2004 | Santa Clara, California, United States

Cost and Performance in Integrated Circuit Creation

27 February 2003 | Santa Clara, CA, United States

Showing 5 of 15 Conference Committees

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