Optical lithography resolution scaling has stalled, giving innovative alternatives a window of opportunity. One important factor that impacts these lithographic approaches is the transition in design style from 2D to 1D for advanced CMOS logic. Just as the transition from 3D circuits to 2D fabrication 50 years ago created an opportunity for a new breed of electronics companies, the transition today presents exciting and challenging time for lithographers. Today, we are looking at a range of non-optical lithography processes. Those considered here can be broadly categorized: self-aligned lithography, self-assembled lithography, deposition lithography, nano-imprint lithography, pixelated e-beam lithography, shot-based e-beam lithography .Do any of these alternatives benefit from or take advantage of 1D layout? Yes, for example SAPD + CL (Self Aligned Pitch Division combined with Complementary Lithography). This is a widely adopted process for CMOS nodes at 22nm and below. Can there be additional design / process co-optimization? In spite of the simple-looking nature of 1D layout, the placement of “cut” in the lines and “holes” for interlayer connections can be tuned for a given process capability. Examples of such optimization have been presented at this conference, typically showing a reduction of at least one in the number of cut or hole patterns needed.[1,2] Can any of the alternatives complement each other or optical lithography? Yes. For example, DSA (Directed Self Assembly) combines optical lithography with self-assembly. CEBL (Complementary e-Beam Lithography) combines optical lithography with SAPD for lines with shot-based e-beam lithography for cuts and holes. Does one (shrinking) size fit all? No, that’s why we have many alternatives. For example NIL (Nano-imprint Lithography) has been introduced for NAND Flash patterning where the (trending lower) defectivity is acceptable for the product. Deposition lithography has been introduced in 3D NAND Flash to set the channel length of select and memory transistors.
The pattern splitting algorithm for 1D Gridded-Design-Rules layout (1D layout) for sub-10 nm node logic devices is shown. It is performed with integer linear programming (ILP) based on the conflict graph created from a grid map for each designated pitch. The relation between the number of times for patterning and the minimum pitch is shown systematically with a sample pattern of contact layer for each node. From the result, the number of times for patterning for 1D layout is fewer than that for conventional 2D layout. Moreover, an experimental result including SMO and total integrated process with hole repair technique is presented with the sample pattern of contact layer whose pattern density is relatively high among critical layers (fin, gate, local interconnect, contact, and metal).
The CMOS logic 22nm node was the last one done with single patterning. It used a highly regular layout style with Gridded Design Rules (GDR). Smaller nodes have required the same regular layout style but with multiple patterning for critical layers. A “line/cut” approach is being used to achieve good pattern fidelity and process margin. As shown in Fig. 1, even with “line” patterns, pitch division will eventually be necessary.
For the “cut” pattern, Design-Source-Mask Optimization (DSMO) has been demonstrated to be effective at the 20nm node and below.[2,3,4] Single patterning was found to be suitable down to 16nm, while double patterning extended optical lithography for cuts to the 10-12nm nodes. Design optimization avoided the need for triple patterning. Lines can be patterned with 193nm immersion with no complex OPC. The final line dimensions can be achieved by applying pitch division by two or four.
In this study, we extend the scaling using simplified OPC to the 7nm node for critical FEOL and BEOL layers. The test block is a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops, scaled from previous experiments.
Simulation results show that for cuts at 7nm logic dimensions, the gate layer can be done with single patterning whose minimum pitch is 53nm, possibly some of the 1x metal layers can be done with double patterning whose minimum pitch is 53nm, and the contact layer will require triple patterning whose minimum pitch is 68nm. These pitches are less than the resolution limit of ArF NA=1.35 (72nm). However these patterns can be separated by a combination of innovative SMO for less than optical resolution limit and a process trick of hole-repair technique. An example of triple patterning coloring is shown in Fig 3. Fin and local interconnect are created by lines and trims. The number of trim patterns are 3 times (min. pitch=90nm) and twice (min. pitch=120nm), respectively. The small number of masks, large pitches, and simple patterns of trims come from the simple 1D layout design.
Experimental demonstration of these cut layers using design optimization, OPC-Lite, and conventional illuminators at the 7nm node dimensions will be presented. Lines were patterned with 193nm immersion with no complex OPC. The final line dimensions (22nm pitch) were achieved with pitch division 4.
Highly regular gridded designs are generally seen as a key component for continued advances in lithographic resolution in a time of limited further progress in lithography hardware . With a given process technology tool set, higher pattern density (lower k1) and quality are achieved using gridded design rules (GDR) in comparison to conventional 2D designs.
GDR is necessary for designs with k1 approaching the theoretical limit ∼ 0.25.
A highly effective implementation of GDR is the
lines+cuts approach discussed in [4, 5, 8] and else- where. Excellent results at very advanced nodes are achieved by this double-patterning process, where lines are created first, then cuts are patterned on top as required by circuit connectivity.
The regular structure of gridded designs offers the opportunity to use an optimized approach to Optical Proximity Correction (OPC), one taking full advantage of the design style to achieve best possible ac- curacy and speed and at the same time small mask file size and good manufacturability. In this work we describe our GDR-tailored OPC tool called OPC- Lite . The OPC-Lite approach is discussed and compared to conventional 2D OPC. Sub-20nm silicon data are shown, validating predictive quality of our simulation and OPC techniques.
Highly regular gridded designs have been generally accepted1 as a key component for continued advances in lithographic resolution in an era of limited further progress in lithography hardware. With a given process technology tool set, higher pattern density (lower k1) and quality are achieved using gridded design rules (GDR) in comparison to conventional 2D designs. GDR is necessary for designs with k1 approaching the theoretical Rayleigh limit ~ 0:25. High pattern densities (fine pitch) and good image quality and manufacturability are achieved by very regular designs Fig. 1, which avoid complex corner structures and pattern density variations typical for conventional 2D designs. In particular lines+cuts implementations of GDR are well-suited for pitch splitting and multiple patterning, where the critical cuts patterns can be easily separated into groups with larger pitch for separate patterning. Very advanced technology nodes thus become possible with conventional lithography technology, see2 for 11nm results.
CMOS logic at the 22nm node and below is being done with a highly regular layout style using Gridded Design Rules (GDR). Smaller nodes have been demonstrated using a “lines and cuts” approach with good pattern fidelity and process margin, with extendibility to ~7nm. In previous studies, Design-Source-Mask Optimization (DSMO) has been demonstrated to be effective down to the 12nm node.[2,3,4,5,6] The transition from single- to double- and in some cases triple- patterning was evaluated for different layout styles, with highly regular layouts delaying the need for multiple-patterning compared to complex layouts. To address mask complexity and cost, OPC for the “cut” patterns was studied and relatively simple OPC was found to provide good quality metrics such as MEEF and DOF.[3,7,8] This is significant since mask data volumes of >500GB per layer are projected for pixelated masks created by complex OPC or inverse lithography; writing times for such masks are nearly prohibitive. In our present work, we extend the scaling using SMO with “OPC Lite” beyond 12nm. The focus is on the contact pattern since a “hole” pattern is similar to a “cut” pattern so a similar technique should be useful. The test block is a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops, scaled from previous studies. The contact pattern is a relatively dense layer since it connects two underlying layers – active and gate – to one overlying layer – metal-1. Several design iterations were required to get suitable layouts while maintaining circuit functionality. Experimental demonstration of the contact pattern using OPC-Lite will be presented. Wafer results have been obtained at a metal-1 half-pitch of 18nm, corresponding to the 11nm CMOS node. Additional results for other layers – FINs, local interconnect, and metal-1 – will also be discussed.
At advanced nodes, CMOS logic is being designed in a highly regular design style because of the resolution limitations of optical lithography equipment. Logic and memory layouts using 1D Gridded Design Rules (GDR) have been demonstrated to nodes beyond 12nm.[1-4] Smaller nodes will require the same regular layout style but with multiple patterning for critical layers.
One of the significant advantages of 1D GDR is the ease of splitting layouts into lines and cuts. A lines and cuts approach has been used to achieve good pattern fidelity and process margin to below 12nm. Line scaling with excellent line-edge roughness (LER) has been demonstrated with self-aligned spacer processing.
This change in design style has important implications for mask making:
• The complexity of the masks will be greatly reduced from what would be required for 2D designs with very complex OPC or inverse lithography corrections.
• The number of masks will initially increase, as for conventional multiple patterning.
But in the case of 1D design, there are future options for mask count reduction.
• The line masks will remain simple, with little or no OPC, at pitches (1x) above 80nm.
This provides an excellent opportunity for continual improvement of line CD and LER. The line pattern will be processed through a self-aligned pitch division sequence to divide pitch by 2 or by 4.
• The cut masks can be done with “simple OPC” as demonstrated to beyond 12nm. Multiple simple cut masks may be required at advanced nodes. “Coloring” has been demonstrated to below 12nm for two colors and to 8nm for three colors.
• Cut/hole masks will eventually be replaced by e-beam direct write using complementary e-beam lithography (CEBL).[7-11] This transition is gated by the availability of multiple column e-beam systems with throughput adequate for high- volume manufacturing.
A brief description of 1D and 2D design styles will be presented, followed by examples of 1D layouts. Mask complexity for 1D layouts patterned directly will be compared to mask complexity for lines and cuts at nodes larger than 20nm. No such comparison is possible below 20nm since single-patterning does not work below ~80nm pitch using optical exposure tools.
Also discussed will be recently published wafer results for line patterns with pitch division by-2 and by-4 at sub-12nm nodes, plus examples of post-etch results for 1D patterns done with cut masks and compared to cuts exposed by a single-column e-beam direct write system.
The CMOS logic 22nm node is being done with single patterning and a highly regular layout style using Gridded Design Rules (GDR). Smaller nodes will require the same regular layout style but with multiple patterning for critical layers. A “lines and cuts” approach is being used to achieve good pattern fidelity and process margin, with extendibility to ~7nm. In previous work, Design-Source-Mask Optimization (DSMO) has been demonstrated to be effective down to the 16nm node.[2,3,4,5] The transition from single- to double- and in some cases triple- patterning was evaluated for different layout styles, with highly regular layouts delaying the need for multiple-patterning compared to complex layouts. To address mask complexity and cost, OPC for the “cut” patterns was studied and relatively simple OPC was found to provide good quality metrics such as MEEF and DOF.[6,7] This is significant since mask data volumes of <500GB per layer are projected for pixelated masks created by complex OPC or inverse lithography; writing times for such masks are nearly prohibitive. In this study, we extend the scaling using SMO with simplified OPC in a technique called “SMOLite” beyond 16nm. The same “cut” pattern is used for each set of simulations, with “x” and “y” locations for the cuts scaled for each node. The test block is a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops. Another approach for scaling the “cut” pattern has also been studied. This involves the use of a hole pitch division process to create a grid template combined with a relatively large “selection” pattern to create cuts at the desired grid locations. Experimental demonstration of the cut approach using SMO-Lite and a grid template will be presented. Wafer results have been obtained at a line half-pitch of 20nm, which corresponds to the gate pitch at the 10nm node.
An SMO whose optimized source shape and mask pattern can be simple is shown. However the simple solution can be
competitive to a solution by complicated source shape and mask pattern. This technology is applied to cut pattern of 1
dimensional GDR layout of 20nm node and below. The simulation under ArF single exposure shows 16nm node of
metal layer and 12nm node of gate layer can be resolved with rectangle mask patterns. For both layers bright field
exposure is used and experimentally positive and negative tone developments are applied for metal layer (island patterns)
and gate layer (cut patterns) respectively. The integrated process through SADP, etching, and so on is shown.
It is found that the simple pattern has lower MEEF than the complicated ones. Applying simple mask pattern MEEF can
be suppressed to be 3~4 even at 16nm node. The SEM images of the masks with simple and complicated shapes show
that it is difficult to reproduce the complicated pattern accurately.
We prepared mask data with various complexities of patterns and evaluated the writing time of an up-to-date EB writer.
The time depends on the shot counts and a typical OPC pattern takes 4 times longer time than rectangle pattern. Since the
cost of writing time is around 20% of the entire cost, the saved cost from OPC pattern to rectangle pattern becomes 15%.
Regarding advanced node of mask with more complicated pattern it takes further longer time and there is an impact on
other technologies of inspection or process. So the saved cost becomes huge.
A roadmap extending far beyond the current 22nm CMOS node has been presented several times.  This roadmap
includes the use of a highly regular layout style which can be decomposed into "lines and cuts." The "lines" can be
done with existing optical immersion lithography and pitch division with self-aligned spacers. The "cuts" can be done
with either multiple exposures using immersion lithography, or a hybrid solution using either EUV or direct-write ebeam.[
4] The choice for "cuts" will be driven by the availability of cost-effective, manufacturing-ready equipment and
Optical lithography improvements have enabled scaling far beyond what was expected; for example, soft x-rays (aka
EUV) were in the semiconductor roadmap as early as 1994 since optical resolution was not expected for sub-100nm
features. However, steady improvements and innovations such as Excimer laser sources and immersion photolithography
have allowed some manufacturers to build 22nm CMOS SOCs with single-exposure optical lithography.
With the transition from random complex 2D shapes to regular 1D-patterns at 28nm, the "lines and cuts" approach can
extend CMOS logic to at least the 7nm node. The spacer double patterning for lines and optical cuts patterning is
expected to be used down to the 14nm node. In this study, we extend the scaling to 18nm half-pitch which is
approximately the 10-11nm node using spacer pitch division and complementary e-beam lithography.
For practical reasons, E-Beam lithography is used as well to expose the "mandrel" patterns that support the spacers.
However, in a production mode, it might be cost effective to replace this step by a standard 193nm exposure and
applying the spacer technique twice to divide the pitch by 3 or 4.
The Metal-1 "cut" pattern is designed for a reasonably complex logic function with ~100k gates of combinatorial logic
and flip-flops. Since the final conductor is defined by a Damascene process, the "cut" patterns become islands of resist
blocking hard-mask trenches. The shapes are often small and positioned on a dense grid making this layer to be the most
critical one. This is why direct-write e-beam patterning, possibly using massively parallel beams, is well suited for this
task. In this study, we show that a conventional shaped beam system can already pattern the 11nm node Metal-1 layer
with reasonable overlay margin.
The combination of design style, optical lithography plus pitch-division, and e-beam lithography appears to provide a
scaling path far into the future.
The CMOS logic 22nm node is being done with single patterning and a highly regular layout style
using Gridded Design Rules (GDR). Smaller nodes will require the same regular layout style but
with multiple patterning for critical layers. A line/cut approach is being used to achieve good pattern
fidelity and process margin, with extendibility to ~7nm.
Design-Source-Mask Optimization (DSMO) has been demonstrated to be effective at the 20nm
node. The transition from single- to double- and in some cases triple- patterning was evaluated for
different layout styles, with highly regular layouts delaying the need for multiple-patterning
compared to complex layouts.
To address mask complexity and cost, OPC for the "cut" patterns was studied and relatively simple
OPC was found to provide good quality metrics such as MEEF and DOF.[3,4,5] This is significant
since mask data volumes of >500GB per layer are projected for pixelated masks created by complex
OPC or inverse lithography; writing times for such masks are nearly prohibitive.
In this study, we extend the scaling using simplified OPC beyond 20nm in small steps, eventually
reaching the 16nm node. The same "cut" pattern is used for each set of simulations, with "x" and "y"
locations for the cuts scaled for each step. The test block is a reasonably complex logic function with
~100k gates of combinatorial logic and flip-flops.
Experimental demonstration of the cut approach using simplified OPC and conventional illuminators
will be presented with comparison to the complex OPC result. MEEF can be measured
experimentally. Lines were patterned with 193nm immersion with no complex OPC. The final
dimensions were achieved by applying pitch division twice.
Using the conditions optimized for the logic block, an SRAM block simulation and experimental
results will also be presented.
The semiconductor industry is moving to highly regular designs, or 1D gridded layouts, to enable scaling to advanced
nodes, as well as improve process latitude, chip size and chip energy consumption.
The fabrication of highly regular ICs is straightforward. Poly and metal layers are arranged into 1D layouts. These 1D
layouts facilitate a two-step patterning approach: a line-creation step, followed by a line-cutting step, to form the desired
IC pattern (See Figure 1).
The first step, line creation, can be accomplished with a variety of lithography techniques including 193nm immersion
(193i) and Self-Aligned Double Patterning (SADP). It appears feasible to create unidirectional parallel lines to at least
11 nm half-pitch, with two applications of SADP for pitch division by four. Potentially, this step can also be
accomplished with interference lithography or directed self assembly in the future.
The second step, line cutting, requires an extremely high-resolution lithography technique. At advanced nodes, the only
options appear to be the costly quadruple patterning with 193i, or EUV or E-Beam Lithography (EBL).
This paper focuses on the requirements for a lithography system for "line cutting", using EBL to complement Optical.
EBL is the most cost-effective option for line cutting at advanced nodes for HVM.
A method to resolve 20nm node of SRAM contact layer whose minimum pitch is 90nm with enough process latitude is
shown. To achieve the target by single exposure under condition of ArF and 1.35 of NA a way to optimize lithography
parameters and layout parameters simultaneously is applied that is called co-optimization. At first the memory cell is
optimized from several viewpoints of device and lithography, and then the entire memory cell block including the array
circuit is optimized. It proves that combination of co-optimization and insertion of SRAF works very well considering
the appropriate printed shape required by the device layout. The co-optimization is compared to such a conventional
method as OPC. The performance is better than conventional OPC. Especially the MEFF is much better and the
evaluation to find the mechanism is shown. It proves that complex patterns with many fragments make MEEF higher.
The superior characteristics of co-optimization are analyzed by the result of Linear Programming that can find the strict
solution. The pixel source shape has become almost same as one by co-optimization. The solution is achieved by binary
mask with simple patterns and the simple source shape. It is crucial for COO.
Achieving 20nm designs with 193nm lithography is difficult even with immersion technology. At 20nm, the metal-1
pitch will be ~64nm, which is well below the 80nm limit for single exposure. In this work we extend on our earlier
results [1-4] to show simulation-based patterning of both SRAMs and logic cells. This is consistent with the emerging
industry consensus that regular designs and multiple exposure techniques will extend 193nm immersion as far down
as 7nm .
The approach relies on 1D Gridded Design Rules with Lines/Cuts (1D GDR LC) selective double patterning. Due to
the highly regular patterns of 1D GDR LC we are able to determine a sharp lithographic optimum as a result of
numerical co-optimization of key layout parameters and lithography settings such as scanner illumination, etc.
including realistic scanner capability.
Critical layers (holes/cuts in 1D GDR LC) consist of a number of identical hole/cut patterns with varying density. We
propose a novel algorithm for full-chip proximity correction of such critical layers. The algorithm consists of 1) a
source-mask optimization step (SMO) to choose optimal scanner settings for a class of designs using standard cells,
followed by 2) a final correction step applied to the entire layout to determine individual sizing for each cut to componsate
for its optical/process environment. This procedure converges rapidly in our test cases producing close to
0nm CD error for each cut. Several test designs including one with approximately 100k transistors using ~20 cells
from a standard cell library including both SRAM and logic cells were used, with good convergence obtained in all
Out procedure is a combination of an SMO step followed by cuts-OPC, the equivalent to OPC applied to cuts of 1D
GDR LC designs. The procedure scales linearly with layout area and can be efficiently applied to full-chip designs.
This paper reports on a simulation study in which we compare different possibilities to find a litho solution for SRAM
and Logic for planar technology nodes between 28 nm and 20 nm, using 193 nm immersion lithography. At these nodes,
it becomes essential to include the layout itself into the optimization process. The so-called gridded layout style is an
attractive candidate to facilitate the printability of several layers, but the benefit of this style, as compared to less
restricted layout styles, is not well quantified for the various technology nodes of interest. We therefore compare it with
two other, less restricted, layout styles, on an identical (small) SRAM-Logic test chip. Exploring a number of paths in the
layout-style - litho-options search space, we try to quantify merits and trade-offs for some of the relevant options. We
will show that layout restrictions are really becoming mandatory for the technology nodes studied in this paper. Other
important enablers for these aggressive nodes are multiple patterning, the use of a local-interconnect layer, negative-tone
development, SMO and the use of optimized free-form illumination sources (from which we also include a few initial
The 20nm generation for logic will be challenging for optical lithography, with a contacted gate pitch of ~82nm and a
minimum metal pitch of ~64nm. A gridded design approach with lines and cuts has previously been shown to allow
optimizing illuminator conditions for critical layers in logic designs. The approach has shown good pattern fidelity
and is expected to be scalable to the 7nm logic node. [2,3,4]
A regular pattern for logic makes the optimization problem straightforward if only standard cells are used in a chip.
However, modern SOC's include large amounts of SRAM memory as well. The proposed approach truly optimizes both,
instead of the conventional approach of sacrificing the SRAM because of logic layouts with bends and multiple pitches.
We consider a design with the logic and SRAMs unified from the beginning. In this case, critical layer orientations as
well as pitches are matched and each of the layers optimized for both functional sets of patterns.
The layout for a typical standard cell using Gridded Design rules is shown in Figure 1a. The Gate electrodes are oriented
in the vertical direction, with Active regions running horizontally. Figure 1b shows a group of SRAM bit cells designed
to be compatible with the logic cell. The Gate orientation and pitch are the same.
Optimization results will be presented for the co-optimization of critical layers for the cells. The Source-Mask
Optimization (SMO) method used can optimize the illumination source  and mask for multiple patterns to improve the
2-D image fidelity and process window while controlling the mask sensitivity. It can incorporate the design intentions
that are implied by Gridded Design rules. SMO will be done to balance complexity of the source and the complexity of
the mask (OPC & MBSRAFs). A flexible approach to the optimization will be introduced.
Gridded Design Rules (GDR) in combination with lines/
cuts double patterning allow imaging of 16nm designs
with 193nm immersion lithography. Highly regular lines/
cut patterns result in the existence of a well-defined optimal
set of lithographic conditions. Since cuts are all of
identical shape and relatively sparse, good image quality
can be obtained with minimal or simplified pattern correction
(OPC equivalent) to compensate for proximity
effects. The use of local interconnect (LI) is shown to offer
further reduction of the required number of cuts and
improves pattern uniformity and image quality.
Critical cut patterns of poly and M1 layers in selected
worst case standard GDR cells were considered. Simultaneous
co-optimization of cut geometry as well as lithographic
conditions such as scanner entrance pupil
illumination was used to bring all cuts within ~1nm of target
CDs at best focus. Optimized conditions significantly
reduced the sensitivity of printed patterns to proximity
effects. Manufacturability was verified using DOF and NILS metrics before and after co-optimization. Experimental lens entrance pupil illumination and lens aberrations including polarization effects were included in the analysis.
In current and next generation nodes lithography is pushed to low k1 lithography imaging regimes. A gridded design
approach with lines and cuts has previously been shown to allow optimizing illuminator conditions for critical layers in
logic designs. The approach has shown good pattern fidelity and is expected to be scalable to the 7nm logic node. 
A regular pattern for logic makes the optimization problem straightforward if only standard cells are used in a chip.[3,4]
However, modern SOC's include large amounts of SRAM as well. The proposed approach truly optimizes both, instead
of the conventional approach of sacrificing the SRAM because of logic layouts with bends and multiple pitches.
The biggest problem in co-optimizing logic cells and SRAM bit cells is the orientation of critical layers. For SRAMs, the
gate and metal1 layers have lines in parallel directions, while in standard cells they are perpendicular. This would require
abandoning dipole illumination for the combined optimization, and at best using some form of quadrupole.
The alternative is to design the logic and SRAMs to be unified from the beginning. In this case, critical layer orientations
as well as pitches could be matched and each of the layers optimized for both functional sets of patterns. Choices of
patterns can be made to achieve DSMO (Design-Source-Mask-Optimization).
In the 28nm to 22nm logic nodes - with contacted pitches from 110nm to 90nm and metal1 pitches from 90nm to 70nm
- one of the questions to answer is when and for which layers double patterning is needed. The limit of single patterning
immersion lithography can only be explored through a smart combination of restricted designs and powerful sourcemask
optimization tools. In this paper a 28nm SRAM block with bit and word line periphery will be used to look at
choices for Design-Source-Mask-Optimization.
Line/space dimensions for 22nm logic are expected to be ~35nm at ~70nm pitch for metal 1. However, the contacted
gate pitch will be ~90nm because of contact-to-gate spacing limited by alignment. A process for self-aligning contact to
gates and diffusions could reduce the gate pitch and hence directly reduce logic and memory cells sizes.
Self-aligned processes have been in use for many years. DRAMs have had bit-line and storage-node contacts defined in
the critical direction by the row-lines. More recently, intra-layer self-alignment has been introduced with spacer double
patterning, in which pitch division is accomplished using sidewall spacers defined by a removable core. This
approach has been extended with pitch division by 4 to the 7nm node.
The introduction of logic design styles which use strictly one-directional lines for the critical levels gives the opportunity
for extending self-alignment to inter-layer applications in logic and SRAMs. Although Gridded Design Rules have been
demonstrated to give area-competitive layouts at existing 90, 65, and 45nm logic nodes while reducing CD
variability, process extensions are required at advanced nodes like 22nm to take full advantage of the regular layouts.
An inter-layer self-aligning process has been demonstrated with both simulations and short-loop wafers. An extension of
the critical illumination step for active and gate contacts will be described.
The 22nm logic node is being approached from at least two different scaling paths. One approach "B" will use Gate and
1x Metal pitches of approximately 80nm, which, combined with the appropriate design style, may allow single exposure
to be used. The other combination under consideration "A" will have a Gate pitch of ~90nm and a 1x Metal pitch of
70nm. Even with immersion scanners, the Rayleigh k1 factor is below 0.32 for 90nm pitch and below the single exposure
resolution limits when the pitch is below 80nm.
Although highly regular gridded patterns help [1,2,3], one of the critical issues for 22nm patterning is Contact and Via
patterning. The lines / cuts approach works well for the poly and interconnect layers, but the "hole" layers have less
benefit from gridded designs and remain a big challenge for patterning.
One approach to reduce the lithography optimization problem is to reconsider the interconnection stack. The Contact
layer is complex because it is connecting two layers on the bottom - Active and Gate - to one layer on the top. Other
layers such as Via-1 only have one layer on the bottom.
A potential solution is a Local Interconnect layer. This layer could be formed as part of the salicide process module,
where a patterned etch would replace the blanket strip of un-reacted metal of the silicide layer. Local interconnect lines
would run parallel to the Gate electrodes, eliminating "wrong-way" lines in the Active layer. Depending on the final
pitch chosen, Local Interconnect could be single or double patterned, or could be done with a self-aligned process plus a
Example layouts of standard cells have shown a significant benefit with local interconnects. For example, the Contact
count is reduced by ~25%, and in many cases Via-1 and Metal-2 usage was eliminated.
The simplified Active pattern, along with reduced contact count and density, permit a different lithography optimization
for the cells designed with Local Interconnect. Metal-1 complexity was also reduced. Details of lithography optimization
results for critical layers, Active, Gate, Local Interconnect, Contact, and Metal-1 will be presented.
We present Interference Assisted Lithography (IAL) as a promising and cost-effective solution for extending lithography. IAL achieves a final pattern by combining an interference exposure with a trim exposure. The implementation of IAL requires that today's 2D random layouts be converted to highly regular 1D gridded designs. We show that an IAL-friendly 6T SRAM bitcell can be designed following 1D gridded design rules and that the electrical characteristics is comparable to today's 2D design. Lithography simulations confirm that the proposed bitcell can be successfully imaged with IAL.
Line/space dimensions for 32nm generation logic are expected to be ~45-50nm at ~90-100nm pitch. It is likely that the
node will begin at the upper end of the range, and then shrink by ~10% to a "28nm" node. For the lower end of the
range, even with immersion scanners, the Rayleigh k1 factor is below 0.32. The 22nm logic node should begin with
minimum pitches of approximately 70nm, requiring some form of double patterning to maintain k1 above 0.25.
Logic patterning has been more difficult than NAND Flash patterning because random logic was designed with complete
"freedom" compared to the very regular patterns used in memory. The logic layouts with bends and multiple pitches
resulted in larger rules, un-optimized illumination, and a poorly understood process windows with little control of
context-dependent "hot spots."
The introduction of logic design styles which use strictly one-directional lines for the critical levels now gives the
opportunity for illumination optimization. Gridded Design Rules (GDR) have been demonstrated to give areacompetitive
layouts at existing 90, 65, and 45nm logic nodes while reducing CD variability. These benefits can be
extended to ≤32nm logic using selective double pass patterning.
Dimensions for 32nm generation logic are expected to be ~45nm. Even with high NA scanners, the k1 factor is below 0.32. Gridded-design-rules (GDR) are a form of restricted design rules (RDR) and have a number of benefits from design through fabrication. The combination of rules and topologies can be verified during logic technology development, much as is done with memories. Topologies which have been preverified can be used to implement random logic functions with "hotspot" prevention that is virtually context-independent. Mask data preparation is simplified with less aggressive OPC, resulting in shorter fracturing, writing, and inspection times. In the wafer fab, photolithography, etch, and CMP are more controllable because of the grating-like patterns. Tela CanvasTM GDR layout was found to give smaller area cells than a conventional 2D layout style. Variability and context independence were also improved.
The 22nm logic technology node with dimensions of ~32nm will be the first node to require some form of pitch-halving.
A unique combination of a Producer APF(R)-based process sequence and GDR-based design style permits
implementation of random logic functions with regular layout patterns. The APF (Advanced Patterning Film) pitch-halving
approach is a classic Self-Aligned Double Patterning scheme (SADP) [1,2,3,4] which involves the creation of
CVD dielectric spacers on an APF sacrificial template and using the spacers as a hardmask for line frequency doubling.
The Tela CanvaTM implements Gridded Design Rules (GDR) using straight lines placed on a regular grid. Logic
functions can be implemented using lines on a half-pitch with gaps at selected locations.
Proc. SPIE. 6798, Microelectronics: Design, Technology, and Packaging III
KEYWORDS: Lithography, Calibration, Etching, Manufacturing, Design for manufacturing, Field effect transistors, Optical proximity correction, Computer aided design, Analog electronics, System on a chip
Device parameter variation across the product die and wafer compromises functionality, performance, and yield of integrated devices increasingly more as technology shrinks into the sub-100 nm range. Such variability is of special importance for System-on-Chip products, affecting e.g., frequency response of the analog/RF blocks. Variability reduction can be accomplished through tightening the manufacturing process, adding technology rules for manufacturability (Design-for-Manufacturability, DFM), or developing parameterized, correct by construction (CBC) design or layout (upstream approach). While so far the best option for variability reduction was to improve process capability without resticting product design (downstream approach), it may no longer be preferred due to the continuously increasing process cost driven by technology shrinks. In this work, we discuss a procedure to separate the variability for a 1D and 2D layout due to the lithography and other combined process effects. We then use this procedure to define design rules for analog/RF layout to minimize parametric variability at the minimal cost of the footprint. These rules can be subsequently used to create the CBC design and layout (upstream approach) such that the process window is
traded for device footprint by the aggressiveness of the resolution enhancement techniques (e.g., optical proximity correction, OPC). Another option for variability reduction, the layout-time addition of design rules or OPC in response to the localized issues in a random layout (hot spots) causes reworks and delays and is not preferred.
Ramping an integrated circuit from first silicon bring-up to production yield levels is a challenge for all semiconductor products on the path to profitable market entry. Two approaches to accelerating yield ramp are presented. The first is the use of laser mask writers for fast throughput, high yield, and cost effective pattern transfer. The second is the use of electrical test to find a defect and identify the physical region to probe in failure analysis that is most likely to uncover the root cause. This provides feedback to the design team on modifications to make to the design to avoid the yield issue in a future tape-out revision. Additionally, the process parameter responsible for the root cause of the defect is forward annotated through the design, mask and wafer coordinate systems so it can be monitored in-line on subsequent lots of the manufacturing run. This results in an improved recipe for the manufacturing equipment to potentially prevent the recurrence of the defect and raise yield levels on the following material. The test diagnostics approach is enabled by the seamless traceability of a feature across the design, photomask and wafer, made possible by a common data model for design, mask pattern generation and wafer fabrication.
The X Architecture is a new way of orienting the interconnect on an integrated circuit using diagonal pathways, as well as the traditional right-angle, or Manhattan, configuration. By enabling designs with significantly less wire and fewer vias, the X Architecture can provide substantial improvements in chip performance, power consumption and cost. Members of the X Initiative semiconductor supply chain consortium have demonstrated the production worthiness of the X Architecture at the 130-nm and 90-nm process technology nodes. This paper presents an assessment of the manufacturing readiness of the X Architecture for the 65-nm technology node. The extent to which current production capabilities in mask writing, lithography, wafer processing, inspection and metrology can be used is discussed using the results from a 65-nm test chip. The project was a collaborative effort amongst a number of companies in the IC fabrication supply chain. Applied Materials fabricated the 65-nm X Architecture test chip at its Maydan Technology Center and leveraged the technology of other X Initiative members. Cadence Design Systems provided the test structure design and chip validation tools, Dai Nippon Printing produced the masks and Canon’s imaging system was employed for the photolithography.
In this paper, we discuss the results from a test chip that demonstrate the manufacturability and integration-worthiness of the X Architecture at the 90-nm technology node. We discuss how a collaborative effort between the design and chip making communities used the current generation of mask, lithography, wafer processing, inspection and metrology equipment to create 45 degree wires in typical metal pitches for the upper layers on a 90-nm device in a production environment. Cadence Design Systems created the test structure design and chip validation tools for the project. Canon’s KrF ES3 and ArF AS2 scanners were used for the lithography. Applied Materials used its interconnect fabrication technologies to produce the multilayer copper, low-k interconnect on 300-mm wafers. The results were confirmed for critical dimension and defect levels using Applied Materials’ wafer inspection and metrology systems.
A resolution enhancement technique suitable for Deep-UV microlithography based on coherent multiple imaging (CMI) will be described. We showed recently that a Fabry-Perot etalon inserted between the mask and the projection lens in an optical stepper is able to simultaneously enhance the resolution and depth of focus of an aerial image. Since the multiple images of the mask pattern created by the etalon are added together coherently, the final image profile is very sensitive to the initial phase conditions. It is possible to simulate this coherent multiple imaging techniques using a simulation model which either superimposes separate output electric fields or by applying an appropriate transmission-phase pupil plane filter in the simulator. The first approach, however, requires a modification of the simulation software which allows output of the electric field profile, while the second approach can be used with a conventional commercial lithography simulator. In this paper computer simulations for isolated and extended contact hole arrays are used to demonstrate that the CMI method can enhance resolution by 18 percent while maintaining or even increasing the DOF of the aerial image. It is also shown that the high intensity side lobes generated by the filter nc abe eliminated by means of a phase shifting mask or by reducing the spatial coherence of the illumination source. The optimum value of spatial coherence was found to be 0.28. In this case the side lobes disappear, and the intensity of the main peaks doubles. The impact of this technique on image intensity is also discussed.
An experimental and theoretical study of a coherent multiple imaging technique that utilizes a Fabry-Perot etalon placed between the photo mask and the projection lens is reported. This technique can enhance both resolution and depth of focus in optical microlithography. A lithography simulation tool, Prolith/2 was used to evaluate the aerial image profile using a complex phase-amplitude pupil-plane filter to simulate the effect of the Fabry-Perot etalon. This work specifically discusses the evaluation of extended periodic patterns, widely used in lithographic simulations. Simulation results are described and compared with experimental data. The impact of Talbot images generated by periodic structures is also described.
Optical microlithography is continuing to play a key role in the fabrication of feature sizes in the 0.25 - 0.1 micrometers regime as the semiconductor industry enters manufacturing of the gigabit chip generation. Several important advances in technologies are needed to achieve this goal. These include the use of excimer lasers and optical resolution enhancement schemes, which will be addressed in this work.
A new concept based on a Fabry-Perot interferometer for the generation of nearly nondiffracting Bessel beams is described experimentally and theoretically, and proposed for potential applications in microlithography such as the fabrication of small isolated patterns. It was demonstrated that the depth of focus can be increased by a factor of about 2, and simultaneously the transverse resolution improved by a factor of 1.6, when using this technique to image contact holes. The theoretical curves show very good agreement with the measured intensity distribution. The properties of simultaneous imaging of two contact holes were also investigated. It was shown experimentally that even in the most critical case (when the first diffraction rings overlap), undesirable interference effects between the adjacent contact holes can be eliminated by means of a phase shifting technique.
The recent trend in microelectronics towards patterning critical feature sizes of 0.25 micrometer and below has motivated the development of microlithography at the deep ultra-violet (DUV) laser wavelengths of 248 and 193 nm. In recent years the performance, reliability, and cost of ownership of excimer light sources have improved. Some key technologies needed for excimer lasers in microlithography include materials issues, gas lifetime, higher repetition rates and improved pulse-to-pulse energy repeatability. An experimental demonstration of a new method to generate nearly nondiffracting Bessel beams using a Fabry-Perot interferometer is described. It is experimentally demonstrated that the DOF can be increased by a factor of 2 and simultaneously the transverse resolution improved by a factor of about 1.6, when using this technique to image contact holes.
Details of an experimental demonstration of a contact hole imaging system are reported in which the depth of focus is increased by a factor of about 3.5 using annular illumination. Due to spatial filtering and nonlinearity of the photoresist, the resolving power was enhanced by 52 percent and it was possible to pattern a 0.28 micrometers contact hole in photoresist deposited on a silica substrate. This technique is capable of fabrication sub-quarter micron holes using excimer laser radiation at 193 nm.
As feature sizes in VLSI circuits extend into the far sub-micron range, new process techniques, such as using phase shifted masks for photolithography, will be needed. Under these conditions, the only means for the circuit designer to design compact and efficient circuits with good yield capabilities is to be able to see the effect of different design approaches on manufactured silicon, instead of solely relying on conservative general design rules. The integrated CAD framework accomplishes this by providing a link between a layout editor (Magic), advanced photolithographic techniques such as phase shifted masks, and a process simulator (Depict). This paper discusses some applications of this tool. A non- conventional process technique involving interferometric phase shifting and off-axis illumination has been evaluated using the tool. Also, a feature of the CAD framework which allows representation of a phase shifted mask, together with its layout analysis capability has been used to compact a piece of layout by inserting phase shifted elements into it.
This paper reports recent progress in achieving subhalf-micron feature sizes with UV laser illumination based on a novel interferometric phase shifting (IPS) technique. In the IPS arrangement, the intensity and amount of phase shift of the shifted beam can be controlled continuously and independently using the same mask. Consequently the method can be considered as a convenient general testbed for practical phase shifting concepts such as strong, weak and attenuated phase shifting. Recent measurements of the lithographic performance of a new concept are reported where phase shifting is combined with off-axis illumination. Experimental as well as simulation data are used to demonstrate this new method. A lithography simulator, Depict from Technology Modeling Associates, Inc. and a related Integrated CAD Framework which is being developed at Rice University was used to simulate and evaluate the performance of the IPS scheme.
This paper reports simulation and experimental details of a novel phase shifting technique based on laser interferometry. Phase shifting is one of the most promising techniques for the fabrication of high density DRAM's. In recent years many kinds of phase shifting methods have been proposed to extend the resolution limit and contrast of image patterns. These techniques however, have several problems that result from the phase shift elements on the mask, especially when applied to UV excimer laser illumination. A new technique will be described that is based on a one-layered reticle which is used as both a reflective and transmissive mask, irradiated from both the front and the back sides. A combination of both off-axis illumination, as well as phase shift are used in the new method. Both the relative path length of the two beams as well as their amplitude can be manipulated in such a way that near 100% contrast can be achieved in the final image. Experimental as well as simulation data are used to demonstrate this new method.
A new phase shifting technique based on interferometry has been developed which is especially suited for deep-UV microlithography. Using only a single layer chromium mask, with no additional phase shift elements, significant resolution and contrast enhancement over conventional transmission lithography can be achieved. Both computer simulations, as well as experiments using a CCD camera and UV photoresist confirm the capabilities of this new approach. Using a relatively simple experimental setup and an illumination wavelength of 355 nm, lines with feature sizes as fine as 0.3 micrometers were achieved.