Advanced process nodes introduce new variability effects due to increased density, new material, new device structures, and so forth. This creates more and stronger Layout Dependent effects (LDE), especially below 28nm. These effects such as WPE (Well Proximity Effect), PSE (Poly Spacing Effect) change the carrier mobility and threshold voltage and therefore make the device performances, such as Vth and Idsat, extremely layout dependent. In traditional flows, the impact of these changes can only be simulated after the block has been fully laid out, the design is LVS and DRC clean. It’s too late in the design cycle and it increases the number of post-layout iteration. We collaborated to develop a method on an advanced process to embed several LDE sources into a LDE kit. We integrated this LDE kit in custom analog design environment, for LDE analysis at early design stage. These features allow circuit and layout designers to detect the variations caused by LDE, and to fix the weak points caused by LDE. In this paper, we will present this method and how it accelerates design convergence of advanced node custom analog designs by detecting early-on LDE hotspots on partial or fully placed layout, reporting contribution of each LDE component to help identify the root cause of LDE variation, and even providing fixing guidelines on how to modify the layout and to reduce the LDE impact.
To provide fabless designers the same advantage as Integrated Device Manufacturer (IDMs), a design-oriented litho
model has been calibrated and an automated lithography (litho) hotspot detection and fixing flow has been implemented
during final routing optimization.
This paper shows how a design-oriented litho model was built and used to automate a litho hotspot fixing design flow.
The model, calibrated and validated against post-OPC contour data at 99%, was embedded into a Litho Physical
Analyzer (LPA) tech file. It allowed the litho contour of drawn layouts to be simulated at full chip level to detect litho
hotspots and to provide fixing guidelines. Automated hotspots fixing was hence made possible by feeding the guidelines
to the fixing tools in an industry based integrated flow. Post-fixing incremental checks were also performed to converge
to a clean design.
Leveraging silicon validation, a model-based variability analysis has been implemented to detect sensitivity to systematic
variations in standard cell libraries using a model-based solution, to reduce performance spread at the cell level and chip
level. First, a simulation methodology to predict changes in circuit characteristics due to systematic lithography and etch
effects is described and validated in silicon. This methodology relies on these two foundations: 1) A physical shape
model predicts contours from drawn layout; 2) An electrical device model, which captures narrow width effects,
accurately reproduces drive currents of transistors based on silicon contours. The electrical model, combined with
accurate lithographic contour simulation, is used to account for systematic variations due to optical proximity effects and
to update an existing circuit netlist to give accurate delay and leakage calculations.
After a thorough validation, the contour-based simulation is used at the cell level to analyze and reduce the sensitivity of
standard cells to their layout context. Using a random context generation, the contour-based simulation is applied to each
cell of the library across multiple contexts and litho process conditions, identifying systematic shape variations due to
proximity effects and process variations and determining their impact on cell delay.
This methodology is used in the flow of cell library design to identify cells with high sensitivity to proximity effects and
consequently, large variation in delay and leakage. The contour-based circuit netlist can also be used to perform accurate
contour-based cell characterization and provide more silicon-accurate timing in the chip-design flow. A cell-variability
index (CVI) can also be derived from the cell-level analysis to provide valuable information to chip-level design
optimization tools to reduce overall variability and performance spread of integrated circuits at 65nm and below.
An automated litho-aware design migration solution has been implemented to enable designers to port existing IP layouts
(custom, library, and block) to nanometer technologies while optimizing layout printability and silicon yield.
With rapidly shrinking technology nodes, the industry consolidation toward fabless or fab-lite manufacturing, demand
for second-sourcing and dramatic increase in cost of IP development, the automation of "vertical" (between nodes) and
'horizontal" (between chip manufacturers) migration becomes a very important task. The challenge comes from the fact
that even within the same technology node design and process-induced rules deviate substantially among different IDMs
and foundries, which leads to costly, error-prone and time consuming design modifications. At the same time, fast and
reliable adjustments to design and ability to switch between processes and chip manufacturers could represent significant
improvement to TTM, and respectively improving ROI. Using conservative rules (or restricted design rules) is not
always a viable option because of the area, performance and yield penalties. The difficulty of migration is augmented by
the fact that design rules are not sufficient to guaranty good printability, maximum process window and high yield.
Model-based detection of lithography-induced systematic yield-limiting defects (a.k.a. hotspots) is becoming a vital part
of the design-for-manufacturing flow for advanced technology nodes at 65nm and below. Driven by customer demand, a
collaborative effort between EDA vendors provides a complete design-for-manufacturing migration solution that allows
sub-65 nanometer designers to comprehensively address the impact of manufacturing variations on design yield and
performance during layout migration. First, the physical hard IP is migrated from its existing 90nm process to a more
advanced 65 and 45 nm processes, resulting in an area-optimized DRC-clean 65nm design retaining the original
hierarchy to facilitate further editing and design verification the original hierarchy is maintained. Then, the design
manufacturability is checked using a model-based hotspot detection solution, applying <i>foundry-certified models</i>. Along
with hotspots, it is also critical for the hotspot detection tool to generate directives on how to modify the layout to fix
hotspots and prevent creation of new hotspots. Several alternative fixing guidelines, ranked by amount of design
perturbation, are generated to provide focus and maximum flexibility to the correction tool. The correction tool reads
hotspot locations, severities along with the fixing guidelines, identifies area to be fixed and converts the fixing guidelines
into geometry constraints. Correction is then done on each area while respecting design rules, managing ripple effects
through multiple layers and maintaining the hierarchy. When all the corrections are completed areas that have been
affected are identified to allow these to be incrementally checked by the lithography verification tool (LPC) and re-assembled.
In case new or residual hotspots are detected, this fix-verify flow iterates over to converge on a DRC and
lithography-compliant design. Usually no more than three iterations are needed to output hotspot-free, DRC and Lithocompliant
design. We present the results of this fully automated lithography-aware migration flow on layout IPs ranging
from 65 nm to 45 nm design and migrated across foundries. Results show substantial layout quality improvements,
reduced design sensitivity to process variability by eliminating hotspots. Run-time and hotspot fixing performance are
The design of integrated circuits (ICs) has been made possible by a simple contract between design and manufacturing: Manufacturing teams encapsulated their process capabilities into a set of design rules such as minimum width and spacing or overlap for each layer, and designers complied with these design rules to get a manufacturable IC. However, since the advent of 130nm technology, designers have to play by the new rules of sub-90nm technologies. The simple design rules have evolved into extremely complex, context-dependent rules. Minimum design rules have been augmented with many levels of yield-driven recommended guidelines. One of the main drivers behind these complex rules is the increase in optical proximity effects that are directly impacting systematic and parametric yields for sub-90nm designs. A design's sensitivity to optical proximity effects increases as features get smaller, however design engineers do not have visibility into the manufacturability of these features.
A genuine design for manufacturing (DFM) solution for designers should provide a fast, easy-to-use and cost-effective solution that accurately predicts the designs sensitivity to shape variations through out the design process. It should identify and reduce design sensitivity by predicting and reducing shape variations. The interface between manufacturing and design must provide designers with the right information to allow them to maximize the manufacturability of their design while shielding them from the effects of resolution enhancement technologies (RET) and manufacturing complexity. This solution should also protect the manufacturing know-how in the case of a fabless foundry flow. Currently, the interface between manufacturing and design solely relies on design rules that do not provide these capabilities.
A common proposition for design engineers in predicting shape variation is to move the entire RET/OPC/ORC into the hands of the designer. However, this approach has several major practicality issues that make it unfeasible, even as a "service" offered to designers:
1- Cost associated with replicating the flow on designer's desktop.
2- The ability of designers to understand RET/OPC and perform lithographic judgments.
3- Confidentiality of the recipes and lithographic settings, especially when working with a foundry.
4- The level of confidence the fab/foundry side has in accepting the resulting RET/OPC.
5- Runtime and data volume explosion.
6- The logistics of reflecting RET/OPC and manufacturing changes.
7- The ability to tie this capability to EDA optimization tools.
In this paper we present a new technique and methodology that overcomes these hurdles and meets both the designer and manufacturing requirements by providing a genuine DFM solution to designers. We outline a new manufacturing-to-design interface that has evolved from rule-based to model-based, and provides the required visibility to the designer on their design manufacturability. This approach is similar to other EDA approaches which have been used to successfully capture complex behavior by using a formulation that has a higher level of abstraction (for example, SPICE for transistor behavior). We will present how this unique approach uses this abstracted model to provide very accurate prediction of shape variations and at the same time, meet the runtime requirements for a smooth integration into the design flow at 90nm and below. This DFM technology enables designers to improve their design manufacturability, which reduces RET complexity, reduces mask cost and time to volume, and increases the process window and yield.
Optical Proximity Correction (OPC) improves image fidelity by adding and subtracting small enhancement shapes from the original pattern data. Although the presence of these small shapes improves the final wafer image quality, it causes an increase in total figure count, longer fracture processing time, and the introduction of sliver figures. These undesirable artifacts can have a negative impact on the mask write time and mask image quality. In this paper we outline alternative OPC treatments which reduce the additional figures produced, and make the layout configurations friendlier to the subsequent mask fabrication phase. These include the alignment of neighboring small shapes during the OPC operation, and the preservation of jog alignment during the biasing phase. Illustrations of example pattern data, and improvement results in terms of figure counts are described.
At 90nm and 65nm, the semiconductor industry is condemned to use 193nm steppers and an overwhelming amount of resolution enhancement techniques (RET). Even when using the best RET solution available, some designs are more amenable to manufacturing than others and their initial yield or startup yield is higher. Design for manufacturing (DFM) has been a hotly discussed topic in both electronic design automation (EDA) and manufacturing communities, and to date much debate remains regarding its precise definition, let alone the solution. However, it is rather intuitive that, whatever the solution is, DFM needs to simultaneously satisfy several objectives in terms of optimizing yield, manufacturing cost and manufacturing friendliness; being transparent to the designer; protecting manufacturing intellectual property (IP); and having a sensible implementation.
In this paper, we will describe a suitable technology that satisfies the data information sharing to ensure that both designers and manufacturers fulfill the expected initial and volume yield expectations. We describe how this technology may be applied pre- and post-tapeout to fulfill both designer and manufactures requirements.
The relentless pursuit of Moore's Law is pushing lithographical equipment to its limits. Extensive use of Resolution Enhancement Technologies (RET) during mask synthesis has allowed the industry to meet demand for density and performance at the 0.13um node and below. RET has been used to sustain the traditional model of printing edges as close as possible to the corresponding edges in the design layout. As technology moves to sub-100nm processes this model is proving to be both challenging and expensive to sustain. Pushing the RET tools to do an aggressive match between layout geometries and the printed pattern results in a large increase in mask cost. Even if this optimization is successful the resulting pattern may not provide the highest possible yield. In previous papers we demonstrated the use of design intent (DI) during mask synthesis to both reduce mask cost and improve yield. In this paper more results are described of how much improvement is possible on mask shot count and sliver count. We also investigate the cell level timing impact of our proposed methodology. Detailed timing results are presented and analyzed along with their impact on the design flow.
As the industry moves to 90nm and below, the size of our process windows are rapidly decreasing. The process window is often not considered during optical proximity correction (OPC) which must match the printed wafer to the original design target for a single process point. This process point is usually at 'best exposure' and 'best defocus'. The results can be verified under different defocus conditions but it is generally assumed that the printed pattern will yield well for a range of defocus and exposure conditions. At 90nm or smaller this assumption is breaking down as the final yield of products is greatly reduced due to low pattern quality under even relatively small process variations.
Instead of optimizing the OPC results using a single model a multi-model approach is proposed where the pattern is optimized using two or more process points. The final printed image is optimized to both minimize the overall CD variations across a process as well as centering this variation with respect to the original target edges in CD critical areas. To maximize the benefits of this technique we also provide more freedom to OPC by making use of design intent to vary the print requirement in different areas of the design. In this paper we describe the process centering methodology and its use of design intent. To evaluate the benefits of this technique a metric is also proposed and used to quantify experimental results. Results are compared with those of a traditional OPC flow.
Dark field Alternating Aperture Phase Shift Mask (AAPSM) technology has developed into an enabling Resolution Enhancement Technology (RET) in the sub-100nm semiconductor device era. As phase shift masks are increasingly used to resolve features beyond just the most critical (for example transistor gates on the poly layer) the probability of phase conflicts (same phase across a feature) has increased tremendously. It has become imperative to introduce design practices that enable the semiconductor fabrication to take advantage of the improved performance that AAPSM delivers. In this paper we analyze the different causes for phase conflicts and the appropriate methods for detecting them, thus building the basis for the Hybrid AAPSM compliance flow. This approach leverages the strengths of existing DRC tools and the AAPSM conversion software. The approach is effective for minimizing the area penalty, thus very effective for density driven designs. By design, it is suited for custom or semi-custom layouts.
The 2001 ITRS roadmap identified the need for tight coupling of design technology with manufacturing technology in order to ensure the successful production of circuits fabricated at the 65nm technology node. The design creation process for 65nm needs to efficiently explore the interaction between device, cell design and manufacturability. Using fast simulation tools for device and lithography simulation and an automated tool for standard cell generation, various process and cell architectural options were investigated. The average and standard deviation of line width had to be matched to the type of application because of the direct relationship between leakage current and performance. Best process latitude for poly line widths is achieved with Full Phase technology. It is shown that by matching design rules to the Full Phase capabilities and using automated layout tools, manufacturabilty could be optizmed without hurting density or performance.
The ITRS roadmap for the 65nm technology node, targets poly gate lengths of 65nm and poly pitches between 140-180nm. In addition, contact overlaps and spacing to diffusion contacts will need to be scaled down. It is very likely that the poly layer will be printed using 193nm high NA steppers and Strong Phase Shift Technologies. Attempts to capture the effect of RET on layout by adding more constraints to the desing rules make it difficult to lay out cells using manual tools and can also lead to sub optimal designs. In this paper we describe a methodology that couples automatic cell generation with Phase shifter insertion and image simulation to allow the design space to be explored more fully.
The 65nm technology node will require a more detailed assessment of the tradeoffs between performance, manufacturability and cost than any previous generation of technology. Circuits fabricated at the 65nm technology node need to use Strong Phase shifting techniques such as Full-Phase and Model based OPC in order to guarantee printability of critical layers, such as the poly layer. We presents a methodology whereby layouts are genrated base don a preliminary set of design rules for 65nm and the process latitude determined using image simulation software. Mask costs were also estiamted base donfigure counts of the required masks. Tradeoffs between mask costs, manufacturibility and density were made by small changes to the design rules. The simultaneous use of tools that integrate the design creation process with mask generation allows far better optimization than current methodology where physical design is separated from the downstream data preparation and processing.
A new methodology for completely phase-shifting a layout with creating local phase conflicts is proposed for lithographic techniques combining one phase-shifting mask and one binary mask exposure. Critical and non-critical areas of the layout are identified and phase conflicts are avoided by splitting the shifter regions from non-critical areas to non-critical areas without crossing critical areas. The out-of-phase splits of the shifter regions are removed using the binary exposure. Simulation results and experimental data collected for 90 nm technology node show no sign of process latitude loss around the areas where the shifters are split. The overlay latitude is commensurate with 90 nm technology scanner requirements (tool to itself). This approach can also be utilized at the cell library level by creating two copies of each cell with forced phase- shifting boundary conditions. The top and bottom of all the cells have the same phase while the left and right side of each cell have opposite phases, in degrees either 0 - 0 and 180 - 180 or 0 - 180 and 180 - 0. This implementation guarantees conflict-free cell creation and placement.