Highly efficient InGaN/GaN LEDs grown on 4- and 8-inch silicon substrates comparable to those on sapphire
substrates have been successfully demonstrated. High crystalline quality of n-GaN templates on Si were obtained by
optimizing combination of stress compensation layers and dislocation reduction layers. The full-width at half-maximum
(FWHM) values of GaN (0002) and (10-12) ω-rocking curves of n-GaN templates on 4-inch Si substrates were 205 and
290 arcsec and those on 8-inch Si substrate were 220 and 320 arcsec, respectively. The dislocation densities were
measured about 2~3×10<sup>8</sup>/cm<sup>2</sup> by atomic force microscopy (AFM) after in-situ SiH<sub>4</sub> and NH<sub>3</sub> treatment. Under the unencapsulated
measurement condition of vertical InGaN/GaN LED grown on 4-inch Si substrate, the overall output power
of the 1.4×1.4 mm<sup>2</sup> chips representing a median performance exceeded 504 mW with the forward voltage of 3.2 V at the
driving current of 350 mA. These are the best values among the reported values of blue LEDs grown on Si substrates.
The measured internal quantum efficiency was 90 % at injection current of 350 mA. The efficiency droops of vertical
LED chips on Si between the maximum efficiency and the efficiency measured at 1A (56.69 A/cm<sup>2</sup>) input current was
Lithography process control becomes increasingly challenging as the design rules shrink. To tackle the issue of
identifying the process window for lithography, we systematically compared three different approaches for 45 nm
process wafer with two variables: Inspection mode (FEM or PWQ) and Analysis methodology (Manual or Design Based
Binning). We found that PWQ + DBB provided the best results.