In this study, we reported on the evaluation result of the optimized high voltage gate patterning in liquid crystal
display (LCD) driver integrated circuit (IC) with its preparation, characterization and composition of each parameter
such as etching gas chemistry, RF power, and pressure. The patterning process of high voltage gate oxide was
performed with the CF<sub>4</sub>/CHF<sub>3</sub>/O<sub>2</sub>/Ar based gas chemistry to avoid the leakage current from high voltage gate stack by
non-uniform remnant gate oxide thickness. Albeit we obtained the minimized fluctuation of gate oxide thickness, the
plasma damage by plasma patterning process affected the leakage current of high voltage gate film stack.
In conclusion, we found that the major parameter for leakage current in high voltage gate stack by DOE method of gate
patterning and achieved that the optimized condition of high voltage gate patterning. To optimize the performance of
high voltage gate oxide, the thickness of remnant oxide must be controlled uniformly in gate patterning for improving
the margin of high voltage gate transistor. Verifying that the patterning performance of physical and electrical
characteristics with analytical tools such as secondary ion mass spectroscopy (SIMS), scanning electron microscopy
(SEM), auger electron spectroscopy (AES) and probe station as well.
We investigated that Shallow Trench Isolation (STI) dry etching process using SiO2 hard-mask and KrF photo-resist in
90nm stand-alone flash device. As shrinkage of design rule, the thickness of photo-resist is reduced because of guarantee
for process margin in photolithographic process, but the etch process margin is smaller. For the reason, the hard-mask system for etch is needed. Generally, the STI dry etching process is composed of two or three steps, such as the ARC etch, the hard-mask etch, and the Si etch. In order to etch multi-stacked layer (ARC, Oxide hard-mask (SiO2), Si<sub>3</sub>N<sub>4</sub> as CMP stopping layer, and Si), we have controlled the parameters of etching (plasma power, gas, and pressure). In the SiO<sub>2</sub> hard-mask and Si<sub>3</sub>N<sub>4</sub> layer etching process, we use a mixture chemistry of CF<sub>4</sub>, CHF<sub>3</sub>, O<sub>2</sub>, and Ar and get an optimized condition for the multi-layer system. The SiO<sub>2</sub> layer is role of mask for Si layer because the selectivity between SiO<sub>2</sub> and Si is superior to others. Finally, we get a good horizontal and vertical profile of STI by using a mixture chemistry of Cl<sub>2</sub>, HBr, and O<sub>2</sub>.
Recently, in order to increase the number of transistors in wafer by small feature size, optical lithography has
been changed to low wavelength from 365nm to 193nm and high NA of 0.93. And further wavelength is aggressively
shifting to 13.5nm for more small feature size, i.e., Extreme Ultra Violet Lithography(EUVL), a kind of Next Generation
Lithography(NGL)<sup>1</sup>. And other technologies are developed such as water immersion(193nm) and photo resist Double
Patterning(DP). Immersion lens system has high NA up to 1.3 due to high n of water(n=1.44 at 193nm), the parameter k1
is process constant, but 0.25 is a tough limit at a equal line and space, if we use immersion lens with 193nm wavelength
than limit of resolution is 37nm. Especially, Double Exposure Technique(DET) process is widely studied because of the
resolution enhancement ability using a same material and machine, despite of process complication. And SADP(Self
Aligned Double Patten) is newly researched for overlay and LER(Line Edge Roughness) enhancement.
In this paper, we illustrate the feasibility of the shift double pattern for 65nm-node flash using a 193nm light
dipole source and the possibility of decrease minimum feature size using a property of silicon shrinkage during thermal