Sub Resolution Assist Features (SRAFs) are now the main option for enabling low-k<sub>1</sub> photolithograpy. These technical challenges for the 45nm node, along with the insurmountable difficulties in EUV lithography, have driven the semiconductor mask-maker into the low-k<sub>1</sub> lithography era under the pressure of ever shrinking feature sizes. Extending lithography towards lower k<sub>1</sub> puts a strong demand on the resolution enhancement technique (RET), and better exposure tool. However, current mask making equipments and technologies are facing their limits. Particularly, due to smaller feature size, the critical dimension (CD) linearity of both main cell patterns and SRAFs on a mask is deviated from perfect condition differently. There are certain discrepancies of CD linearity from ideal case. For example, as the CD size gets smaller, the bigger CD discrepancy is to be.
There are many technologies, such as hard-mask process and negative-resist process and so on. One of them is an assist feature correction, which can be applied to achieve better CD control. In other words, in order to compensate this CD linearity deviation, the new correction algorithm with SRAFs is applied in data process flow. In this paper, we will describe in detail the implement of our study and present results on a full 65nm node with experimental data.
As the minimum feature size gets smaller, the use of optical proximity correction (OPC)
becomes more aggressive. The time for mask data preparation dramatically increases.
The increase in the number of small size patterns in design causes the increase of Mask Rule
Check (MRC) error. It brings the need for checking the error between mask fab and Taped-out
customers. Therefore, the Turn-Around Time (TAT) is enlarged.
MRC offers not only the rule check but also the violated-pattern-correction to satisfy the quality
requested by the customers.
In this paper, we suggest a new MRC flow by using new MRC tool that carrys out MRC over
various input of e-beam data and handles the MRC output data.
In case of the violated pattern which approaches Mask Constraint we expand violated pattern
size for pattern correction. And the elimination method can be applied to very small pattern.
We describe how well preformed differently in mask exposure time and inspection capability.
As the critical dimension (CD) becomes smaller, various resolution enhancement techniques (RET) are widely adopted. In developing sub-100nm devices, the complexity of optical proximity correction (OPC) is severely increased and applied OPC layers are expanded to non-critical layers. The transformation of designed pattern data by OPC operation causes complexity, which cause runtime overheads to following steps such as mask data preparation (MDP), and collapse of existing design hierarchy. Therefore, many mask shops exploit the distributed computing method in order to reduce the runtime of mask data preparation rather than exploit the design hierarchy. Distributed computing uses a cluster of computers that are connected to local network system. However, there are two things to limit the benefit of the distributing computing method in MDP. First, every sequential MDP job, which uses maximum number of available CPUs, is not efficient compared to parallel MDP job execution due to the input data characteristics. Second, the runtime enhancement over input cost is not sufficient enough since the scalability of fracturing tools is limited. In this paper, we will discuss optimum load balancing environment that is useful in increasing the uptime of distributed computing system by assigning appropriate number of CPUs for each input design data. We will also describe the distributed processing (DP) parameter optimization to obtain maximum throughput in MDP job processing.