Time-to-mask (ttm) has been growing exponentially in the subwavelength era with the increased application of advanced RET's (Resolution Enhancement Technology). Not only are a greater number of design/mask layers impacted but more-and-more layers also have more severe restrictions on critical dimension uniformity (CDU) despite operating at a very low k<sub>1</sub> factors necessitating rigorous but practical tolerancing. Furthermore, designs are also more complex, may be built up from blocks spanning different design styles, and occupy increasingly-large Rayleigh field areas. Given these factors and scales, it's no wonder that the cycle time for verification of a design following RET, is growing however it is doing so exponentially and that this is a critical factor impeding ttm. Until an unambiguously interprable and standard Mask Design Rule (MaskDR) set is created, neither the designer nor the mask supplier can reliably verify manufacturability of the mask for the simple reason that ambiguity and inter-rule conflict are at the source of the problem and that the problem increasingly requires cooperation spanning a large ecosystem of tool, IP, and mask suppliers all needing to essentially speak the same language. Since the 130 nm node, Texas Instruments has enforced a strict set of mask rule checks (MRCs) in their mask data preparation (MDP) flow based on MaskDRs negotiated with their mask suppliers. The purpose of this effort has been to provide an <i>a-priori</i> guarantee that the data shipped to the mask shop can be used to manufacture a mask reliably and with high yield both from a mask standpoint and from the silicon standpoint. As has been reported earlier, mask manufacturing rules are usually determined from assumed or experimentally acquired/validated mask-manufacturing limits. These rules are then applied during RET/MDP data treatment to guide and/or limit pattern correction strategies. With increasing RET and low-k<sub>1</sub> lithography challenges, the importance of MRCs compounds. Furthermore, it will be necessary to comprehend certain MRC restrictions in the design flow as well as in the RET and MDP space. While mask tool manufacturers will need to be able specify tools specifications relevant to the MRCs for a particular mask shop flow, software tool suppliers, such as for RET, need to do so as well with tools which comprehend, check for, and enforce MRCs consistently. IDMs, foundaries, mask shops, EDA companies and tool suppliers will need a common language for the discussion on MaskDRs and MRCs in order to reach unambiguous convergence. Experience at Texas Instruments shows that accurate description, specification, and interpretation of MaskDRs and applying the associated MRCs is critical to a successful advanced mask technology strategy. This paper proposes the creation of a standard MaskDR lexicon. The goal of such a lexicon is the standardization of MaskDRs and their definitions such that interested parties from various mask-related disciplines can discuss, negotiate, specify, test and enforce MaskDRs unambiguously. We further propose that this standard be machine readable and directly usable without the necessity for intermediate interpretations. This lexicon would allow the designers, IDMs, foundaries, mask suppliers, and equipment suppliers to unambiguously negotiate and agree upon mask manufacturability requirements for their particular application.
There is a growing realization of the need for highly integrated solutions enabled by new bi-directional data 'pipes' between design and manufacturing. Traditional EDA applications should be able to communicate and collaborate with yield analysis software. Simply adding such capabilities to existing EDA applications is not feasible. Thus, there is a need for an infrastructure that would enable such interaction in a standard way. We call this infrastructure the DFM Platform.
In this article we present new approach to building such a platform. Brief descriptions of potential applications follow the platform architecture. "Via analysis" application includes test chips capabilities, critical area and critical parameter analysis to predict yield for a real design. The "DFM Cell Grading" module applies the concept of DFM to IP Libraries.
We consider modern design for manufacturing (DFM) as a manifestation of IC industry re-integration and intensive cost management dynamics. In that regard DFM is somewhat different from so-called design for yield (DFY) which essentially focuses on productivity (yield) management (that is not to say that DFM and DFY do not have significant overlaps and interactions).
We clearly see the shaping of a new "full-chip DFM" infrastructure on the background of the "back to basics" design-manufacturing re-integration dynamics. In the presented work we are focusing on required DFM-efficiencies in a "foundry-fabless" link. Concepts of "virtual prototyping of manufacturing", "design process optimization", and "foundry-portable DFM" models are explored. Both senior management of the industry and leading design groups finally realize the need for a radical change of design styles. Some of the DFM super-goals are to isolate designers from process details and to make designs foundry portable. It requires qualification of designs at different foundries. In their turn, foundries specified and are implementing a set of DFM rules: "action-required", "recommended", and "guidelines" while asking designers to provide netlist and testing information. Also, we observe strong signs of innovation coming back to the mask industry. Powerful solutions are emerging and shaping up toward mask-centered IP as a business.
While it seems that pure-play foundries have found their place for now in the "IDM+" model (supporting manufacturing capacity of IDMs) it is not obvious how sustainable the model is. Wafer as a production unit is not sufficient anymore; foundries are being asked by large customers to price products in terms of good die. It brings back the notion of the old ASIC business model where the foundry is responsible for dealing with both random and systematic yield issues for a given design. One scenario of future development would be that some of the leading foundries might eventually transform themselves into IDMs. Another visible trend: some of the manufacturing capacities started to diversify business by providing services for new emerging markets (for example, new energy and medicine applications). Finally it is very unclear what’s going to happen to fabless players.
We continue building on the "Think SPICE again!" methodology introduced last year and expanding on previous platforms' discussion. Model expression of DFM, most probably, will be supplied by the equipment suppliers and yield management community. Actual content for a design intent model will be provided by manufacturing. Much like SPICE it describes the behavior and not what the actual measurement in manufacturing is. When the model is available and populated, a design automation solution can be created that will allow a designer to extract, analyze, simulate, and optimize the circuit prior to handoff to manufacturing.
Mask manufacturing rules are usually determined from assumed or experimentally acquired mask-manufacturing limits. These rules are then applied during resolution enhancement data treatment to guide and/or limit pattern correction strategies. This technique can be highly reactive and may not allow a careful tradeoff between the mask making capability and the end user needs. We have explored techniques to develop mask manufacturability rules in the context of wafer lithography and device needs.
In this paper, we consider methods to improve the capture and usage of mask making information for resolution enhancement by applying a novel test mask and design, which is tied to a process modeling software. Mask manufacturing models are established from the test maks design and these models are applied to generate geometrical rules and continuous models linking the mask making capability to the lithography requirements. The analysis of mask manufacturing constraints is extended into the device domain through yield prediction tools that capture the impact of lithography variability on device performance.
We find techniques allowing a more dynamic generation of relevant mask making constraints that can optimize both yield and cycle time in the resolution ehancement process flow. Toward this, usage cases are highlighted to illustrate the interaction of specific design layouts and our mask manufacturability.
In this paper we review current design-to-silicon manufacturing challenges and complexities confronting the IC design and manufacturing worlds as the industry prepares for sub-100nm technology node IC production and discuss a simplifying infrastructure and various principles for reducing and managing these complexities. Rapidly increasing overall complexity spanning all elements of the design- through-silicon 'ecosystem' and entanglement of the intricacies of traditionally separable design and manufacturing process technical disciplines is increasingly evident in long-loop design-mask-FAB iterations portending a widening of the design-productivity gap and an impact on the cost-effectiveness and productivity of the IC industry. Using the concept of 'technology overshoot' we conclude that the IC industry must broaden its development efforts and diversify investments to include those of building a robust and inherently simplifying interface infrastructure between design and manufacturing and to enable the efficiencies required of a maturing industry. We also explore the concept of modularity and how other mature industries have employed it to optimize efficiencies and investments and conclude that while the design and manufacturing worlds have practiced a number of fundamental concepts of modularity - the overall desegregation of the industry as a whole as case in point - a consistent, well-planed architecture for managing the interface between the two worlds has not yet been employed; hindering the development and migration of much needed productivity and cost-effectiveness enhancements. We then discus the impact of these factors on the industry in light of sub-wavelength era lithography resolution enhancement technologies and related manufacturing process and device physics issue, which increasingly impact the design flow. Recognizing that significant improvement to the design-silicon manufacturing interface is required, lastly we discuss a solution in the form of a new industry initiative called GDS-3. In our findings we acknowledge that the IC industry has already developed a solution, called OpenAccess, to a similar problem in the design space having to do with interoperability between design automation tools. We relate this work to the issues being faced between design and manufacturability and draw our final conclusion that the new design-to-manufacturing infrastructure should be an augmentation of the design community's Open Access initiative.
Optical interconnects provide wide bandwidth, lowloss, and high fanout as compared to those for traditional electrical interconnects. In the past years many high performance optoelectronic circuits have been demonstrated. However, most of them require complicated process and exotic devices. To make optical interconnects in real system and commercial use, circuits utilizing manufacturable, robust, and low-cost technology have to be realized. Ion implanted GaAs MESFETs provide great promise due to their simplicity in manufacturing and their high speed performance. The optical characteristics of GaAs materials also make this technology favorable in realizing low-cost, high-performance OEICs.