Design weak points, or “hotspots” remain a leading issue in advanced lithography. These often lead to unexpected critical dimension (CD) behavior, degradation of process window and ultimately impact wafer yield. Industry technology development focus on hotspot detection has included full chip lithography simulation and machine learning-based hotspot analysis. Most recently, the machine learning approach is gaining attention because it is faster and more practical than lithography simulation-based hotspot detection. The machine learning case is a feedback approach based on previous known design hotspots. Conversely, the simulation method has the benefit of proactively detecting hotspots in a new design regardless of historical data. However, full chip simulation requires resources in calculating time, computing power and additional time-to-market that render it impractical in some scenarios. As design rules shrink, advanced mask designs have significantly increased in complexity due to Resolution Enhancement Techniques (RET) such as Source Mask Optimization (SMO), advanced Optical Proximity Correction (OPC) and high transmission attenuating mask films. This complicates hotspot detection by existing OPC verification tools or rigorous lithographic simulation with wafer resist model. These resultant complex mask geometries make OPC optimization and hotspot detection using post design very difficult. In this paper, we will demonstrate the limitation of traditional hotspot detection technology. Typical OPC tools use simple techniques such as single Gaussian approximations on the design, such as corner rounding, to take the mask process impact to the geometry into account. We will introduce a practical lithography hotspot identification method using mask process model. Mask model-based hotspot detection will be used to precisely identify lithography hotspots and will provide the information needed to improve hotspots’ lithographic performance.
Extreme ultraviolet lithography (EUVL) is entering an industry production phase for 7nm logic and is under development for next node logic and memory applications. A key benefit of EUVL for logic interconnect lithography comes from the ability to pattern the metal layer at aggressive pitch using a single exposure. We report here a mask process compatible with a 30nm pitch patterning module for the demanding sub 7nm node, single expose interconnect application. We found a large increase in mask to wafer image transfer sensitivity during the 32nm to 30nm pitch shrink development that led to increases in stochastic and systematic wafer defect generation mechanisms. In this work, we describe our steps to characterize, model and improve the mask related factors that reduce this sensitivity as part of a successful 30nm pitch patterning module demonstration. High resolution wide area electron beam mask inspection alongside a suite of advanced mask characterization and optimization(AMCO)tools were key elements in understanding mask process gaps and improvement opportunities. Critical mask parameters optimized in closed loop with wafer response included two and three dimensional pattern fidelity, line roughness and spatial variability. Mask critical dimension targeting was found to be a critical factor for delivering the yielding 30nm pitch wafer process and this targeting was tuned dynamically through mask and wafer co-optimization. Finally, the role of wafer anchored process simulation proved an invaluable guide for linking various mask error source mechanisms to the wafer response.
Design weak points that have narrow process window and limits wafer yield, or hotspots, continue to be a major issue in semiconductor photolithography. Resolution enhancement techniques (RET) such as advanced optical proximity correction (OPC) techniques and source mask optimization (SMO) are employed to mitigate these issues. During yield ramp for a given technology node, full-chip lithography simulation, pattern-matching and machine learning are adopted to detect and remedy the weak points from the original design , . This is typically an iterative process by which these points are identified in short-loop lithography testing. Design retarget and/or OPC modifications are made to enhance process window until the yield goal is met. This is a high cost and time consuming process that results in a slow yield ramp for existing production nodes and increased time to market (TTM) for new node introduction. Local hotspot correction through mask and wafer harmonization is a method to enhance wafer yield with low cost and short cycle time compared to the iterative method. In this paper, a fast and low cost approach to hotspot correction is introduced. Hotspots were detected on wafer after OPC and characterized by using advanced mask characterization and optimization (AMCO) techniques. Lithographic simulations and AIMS measurement were used to verify the hotspot correction method. Finally, the validity of this new approach was evaluated by process window analysis and circuit probe yield test at wafer.