The initial readiness of EUV patterning was demonstrated in 2016 with IBM Alliance's 7nm device
technology. The focus has now shifted to driving the 'effective' k1 factor and enabling the second
generation of EUV patterning. Thus, Design Technology Co-optimization (DTCO) has become a critical
part of technology enablement as scaling has become more challenging and the industry pushes the limits
of EUV lithography. The working partnership between the design teams and the process development
teams typically involves an iterative approach to evaluate the manufacturability of proposed designs,
subsequent modifications to those designs and finally a design manual for the technology. While this
approach has served the industry well for many generations, the challenges at the Beyond 7nm node require
a more efficient approach. In this work, we describe the use of “Design Intent” lithographic layout
optimization where we remove the iterative component of DTCO and replace it with an optimization that
achieves both a “patterning friendly” design and minimizes the well-known EUV stochastic effects.
Solved together, this “design intent” approach can more quickly achieve superior lithographic results while
still meeting the original device’s functional specifications.
Specifically, in this work we will demonstrate “design intent” optimization for critical BEOL layers using
design tolerance bands to guide the source mask co-optimization. The design tolerance bands can be either
supplied as part of the original design or derived from some basic rules. Additionally, the EUV stochastic
behavior is mitigated by enhancing the image log slope (ILS) for specific key features as part of the overall
optimization. We will show the benefit of the “design intent approach” on both bidirectional and
unidirectional 28nm min pitch standard logic layouts and compare the more typical iterative SMO
approach. Thus demonstrating the benefit of allowing the design to float within the specified range.
Lastly, we discuss how the evolution of this approach could lead to layout optimization based entirely on
some minimal set of functional requirements and process constraints.
The utilization of a cut-mask in semiconductor patterning processes has been in practice for logic devices since the inception of 32nm-node devices, notably with unidirectional gate level printing. However, the microprocessor applications where cut-mask patterning methods are used are expanding as Self-Aligned Double Patterning (SADP) processes become mainstream for 22/14nm fin diffusion, and sub-14nm metal levels. One common weakness for these types of lithography processes is that the initial pattern requiring the follow-up cut-mask typically uses an extreme off-axis imaging source such as dipole to enhance the resolution and line-width roughness (LWR) for critical dense patterns. This source condition suffers from poor process margin in the semi-dense (forbidden pitch) realm and wrong-way directional design spaces. Common pattern failures in these limited design regions include bridging and extra-printing defects that are difficult to resolve with traditional mask improvement means. This forces the device maker to limit the allowable geometries that a designer may use on a device layer.
This paper will demonstrate methods to expand the usable design space on dipole-like processes such as unidirectional gate and SADP processes by utilizing the follow-up cut mask to improve the process window. Traditional mask enhancement means for improving the process window in this design realm will be compared to this new cut-mask approach. The unique advantages and disadvantages of the cut-mask solution will be discussed in contrast to those customary methods.
As technology development advances into deep-sub-wavelength nodes, multiple patterning is becoming more essential to achieve the technology shrink requirements. Recently, Optical Proximity Correction (OPC) technology has proposed simultaneous correction of multiple mask-patterns to enable multiple patterning awareness during OPC correction. This is essential to prevent inter-layer hot-spots during the final pattern transfer. In state-of-art literature, multi-layer awareness is achieved using simultaneous resist-contour simulations to predict and correct for hot-spots during mask generation. However, this approach assumes a uniform etch shrink response for all patterns independent of their proximity, which isn’t sufficient for the full prevention of inter-exposure hot-spot, for example different color space violations post etch or via coverage/enclosure post etch.
In this paper, we explain the need to include the etch component during multiple patterning OPC. We also introduce a novel approach for Etch-aware simultaneous Multiple-patterning OPC, where we calibrate and verify a lumped model that includes the combined resist and etch responses. Adding this extra simulation condition during OPC is suitable for full chip processing from a computation intensity point of view. Also, using this model during OPC to predict and correct inter-exposures hot-spots is similar to previously proposed multiple-patterning OPC, yet our proposed approach more accurately corrects post-etch defects too.
As technology development advances into deep submicron nodes, it is very important not to ignore any systematic effect that can impact CD uniformity and the final parametric yield. One important challenge for OPC is in choosing the proper etch process correction flow to compensate for design-to-design etch shrink variations. Although model-based etch compensation tools have been commercially available for a few years now, rules-based etch compensation tables have been the standard practice for several nodes. In our work, we study the limitations of the rules-based etch compensation versus model-based etch compensation. We study a 10nm process and provide the details of why using Model-Based Etch Process Correction can achieve up to 15% improvement in final CD uniformity. We also provide a systematic methodology for identifying the proper etch correction technique for a given etch process and assessing the potential accuracy gain when switching to the model-based etch correction.
Dummy fill insertion is a necessary step in modern semiconductor technologies to achieve homogeneous
pattern density per layer. This benefits several fabrication process steps including but not limited to Chemical
Mechanical Polishing (CMP), Etching, and Packaging. As the technology keeps shrinking, fill shapes become more
challenging to pattern and require aggressive model based optical proximity correction (MBOPC) to achieve better
design fidelity. MBOPC on Fill is a challenge to mask data prep runtime and final mask shot count which would
affect the total turnaround time (TAT) and mask cost. In our work, we introduce a novel flow that achieves a robust
and computationally efficient fill handling methodology during mask data prep, which will keep both the runtime
and shot count within their acceptable levels. In this flow, fill shapes undergo a smart MBOPC step which improves
the final wafer printing quality and topography uniformity without degrading the final shot count or the OPC cycle
runtime. This flow is tested on both front end of line (FEOL) layers and backend of line (BEOL) layers, and results
in an improved final printing of the fill patterns while consuming less than 2% of the full MBOPC flow runtime.