To realize HVM (High Volume Manufacturing) with CP (Character Projection) based EBDW, the shot count
reduction is the essential key. All device circuits should be composed with predefined character parts and we call this
methodology “CP element based design”. In our previous work, we presented following three concepts .
1) Memory: We reported the prospects of affordability for the CP-stencil resource.
2) Logic cell: We adopted a multi-cell clustering approach in the physical synthesis.
3) Random interconnect: We proposed an ultra-regular layout scheme using fixed size wiring tiles containing repeated
tracks and cutting points at the tile edges.
In this paper, we will report the experimental proofs in these methodologies.
In full chip layout, CP stencil resource management is critical key. From the MCC-POC (Proof of Concept) result ,
we assumed total available CP stencil resource as 9000um2. We should manage to layout all circuit macros within this
restriction. Especially the issues in assignment of CP-stencil resource for the memory macros are the most important as
they consume considerable degree of resource because of the various line-ups such as 1RW-, 2RW-SRAMs, Resister
Files and ROM which require several varieties of large size peripheral circuits. Furthermore the memory macros
typically take large area of more than 40% of die area in the forefront logic LSI products so that the shot count increase
impact is serious. To realize CP-stencil resource saving we had constructed automatic CP analyzing system. We
developed two types of extraction mode of simple division by block and layout repeatability recognition. By properly
controlling these models based upon each peripheral circuit characteristics, we could minimize the consumption of CP
stencil resources. The estimation for 14nm technology node had been performed based on the analysis of practical
memory compiler. The required resource for memory macro is proved to be affordable value which is 60% of full CP
stencil resource and wafer level converted shot count is proved to be the level which meets 100WPH throughput.
In logic cell design, circuit performance verification result after the cell clustering has been estimated. The cell
clustering by the acknowledgment of physical distance proved to owe large penalty mainly in the wiring length. To
reduce this design penalty, we proposed CP cell clustering by the acknowledgment of logical distance.
For shot-count reduction of random interconnect area design, we proposed a more structural routing architecture which
consists of the track exchange and the via position arrangement. Putting these design approaches together, we can design
CP stencils to hit the target throughput within the area constraint.
From the analysis for other macros such as analog, I/O, and DUMMY, it has proved that we don’t need special CP
design approach than legacy pattern matching CP extraction.
From all these experimental results we get good prospects to the reality of full CP element based layout.
For accurate analysis of circuit performance, an understanding on-chip gate length variation is required. Non-systematic
OCLV was measured by SEM and the results were analyzed after being divided into local and global factors. Simple
empirical models of global and local variations were proposed, and fitting was done. In the fitting, measured mask
variation was used, and on-chip variation of focus, dose, and LWR were fitting parameters. The fit of our model was
very consistent with experimental result. Prediction of global and local variation using lithographic characters of
patterns, such as EL, DOF, and MEEF, was enabled.
We proposed a design-friendly DFM rule intended to improve circuit performance. To reduce variations in the gate length, we applied active usage of preferred gate spaces and optimized the lithographic conditions. We selected the spaces to take into account the layouts that are used most frequently in actual design, so that many designers who are worrying about chip area and performance can follow the rule. The effect of our method was evaluated for 65-nm node technology. From the viewpoint of gate length, parallel usage of design following the rule and optimization lead to an 8% decrease in variation, and a 38% decrease in the mean difference from the targeted gate length. We also evaluated the effect on delays using an accurate method that can treat both statistical and systematic variation. The difference in the average delay from the targeted value was reduced from about 1% to less than 0.1%, and a 10% improvement in delay variation was observed.
Local flare is caused by scattered light from lens surfaces, and it causes the printed line width to vary or degrades printing accuracy. Consequently, local flare must be taken into account when manufacturing IC devices that use lithography generations of less than 90 nm. In particular, an OPC (Optical Proximity Correction) tool with the ability to compensate local flare effects is required to maintain a high degree of printing accuracy. For model-based OPC to work properly, the predicted line width or shape given by a simulator should show good agreement with experimental results. Local flare intensity is calculated from the optical intensity in the absence of local flare, in order to take diffraction effects into account. An aerial image considering local flare effects is given simply by the sum of optical intensity and local flare intensity. To account for local flare effects in a practical manner, the local flare intensity is converted into a variation in the threshold for OPC/DRC (Design Rules Checking) that predicts the desired shape. This paper describes the impact of local flare, the simulation model including local flare effects, and its results. The simulation results show good agreement with the experimental results, indicating that effective OPC/DRC using this method is possible.