A readout channel based on continuous-time incremental sigma-delta analog-to-digital converter for FET-based terahertz (THz) imaging applications was implemented in a 0.15 μm standard CMOS technology. The designed readout circuit is suitable for implementation in pixel arrays due to its compact size and power consumption. The system-level analysis used to define the modulator parameters and to specify its analog building blocks is presented. The loop filter has been realized by using a Gm-C integrator. Circuit linearization techniques have been implemented to improve the linearity of the transconductor cell and reduce the impact of parasitic capacitances. Moreover, chopper stabilization technique is adopted in the loop filter, significantly reducing the low-frequency flicker noise thereby preserving the Noise Equivalent Power (NEP) of the FET detector within the required specifications of minimum detectable signal. The resulting input referred noise voltage is 87.5 nV/√Hz . The incremental ADC achieves 68-dB peak signal-to-noise-and-distortion-ratio (SNDR), equivalent to 11 bits effective resolution over 1 kHz signal bandwidth at 1 MHz sampling frequency. In order to meet the requirements of large sensor arrays, a first order architecture is realized. This leads to lower area occupancy and power consumption. The readout circuit draws 80 μW of power from a supply voltage of 1.8 V. The channel occupies an area of 90 x 273μm<sup>2</sup>.