This paper presents a short-distance reconfigurable high-speed optical interconnects architecture employing a Vertical
Cavity Surface Emitting Laser (VCSEL) array, Opto-very-large-scale-integrated (Opto-VLSI) processors, and a
photodetector (PD) array. The core component of the architecture is the Opto-VLSI processor which can be driven by
digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output
ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL
array and 1×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the
crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the
Opto-VLSI processors and driving the latter with optimal steering phase holograms.
In this paper, we propose and demonstrate a new MicroPhotonic structure for optical packet header recognition based on the integration of an optical cavity, optical components and a photoreceiver array. The structure is inherently immune to optical interference thereby routing an optical header within optical cavities to different photoreceiver elements to generate the autocorrelation function, and hence the recognition, of the header using simple microelectronic circuits. The proof-of-concept is simulated and experimentally demonstrated.
In this paper, we propose a time-token multi-Gb/s Wavelength Division Multiplexing Fibre Distributed Data Interface (WDM/FDDI) architecture and examine its throughput efficiency and delay under heavy load for different network configuration using discrete event simulator.